AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 127

• Manufacturer Part Number: AU80610004653AAS LBMG
• Description: MPU, ATOM PROCESSOR, N450, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - N400r

Specifications of AU80610004653AAS LBMG

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Processor Configuration Registers
1.9.3
Datasheet
15:11
Bit
10
9
8
7
6
5
4
3
2
Access
PCICMD2 - PCI Command
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This 16-bit register provides basic control over the IGD's ability to respond to PCI
cycles. The PCICMD Register in the IGD disables the IGD PCI compliant master
accesses to main memory.
RW
RW
RO
RO
RO
RO
RO
RO
RO
RO
Default
Value
00h
0b
0b
0b
0b
0b
0b
0b
0b
0b
RST/PWR
FLR, Core
FLR, Core
Core
Core
Core
Core
Core
Core
Core
Core
Reserved
Interrupt Disable (INTDIS):
DO_INTx messages will not be sent to DMI.
Fast Back-to-Back (FB2B):
SERR Enable (SERRE):
Address/Data Stepping Enable (ADSTEP):
Parity Error Enable (PERRE):
belongs to the category of devices that does not corrupt
programs or data in system memory or hard drives, the
IGD ignores any parity error that it detects and continues
with normal operation.
Video Palette Snooping (VPS):
Memory Write and Invalidate Enable (MWIE):
and invalidate commands.
Special Cycle Enable (SCE):
cycles.
Bus Master Enable (BME):
This bit controls the IGD's response to bus master
accesses.
This bit disables the device from asserting INTx#.
0: Enable the assertion of this device's INTx# signal.
1: Disable the assertion of this device's INTx# signal.
Not Implemented. Hardwired to 0.
Not Implemented. Hardwired to 0.
Not Implemented. Hardwired to 0. Since the IGD
This bit is hardwired to 0 to disable snooping.
Hardwired to 0. The IGD does not support memory write
This bit is hardwired to 0. The IGD ignores Special
0: Disable IGD bus mastering.
1: Enable the IGD to function as a PCI compliant master.
0/2/0/PCI
4-5h
0000h
16 bits
Not Implemented. Hardwired to 0.
RO; RW;
Description
127