AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 34

• Manufacturer Part Number: AU80610004653AAS LBMG
• Description: MPU, ATOM PROCESSOR, N450, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - N400r

Specifications of AU80610004653AAS LBMG

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.5.3
34
PCICMD - PCI Command
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Since processor Device 0 does not physically reside on PCI_A many of the bits are not
implemented.
15:10
Bit
9
8
7
Access
RW
RO
RO
RO
Default
Value
00h
0b
0b
0b
0/0/0/PCI
4-5h
0006h
16 bits
RO; RW;
(Sheet 1 of 2)
RST/
PWR
Core
Core
Core
Core
Reserved
Fast Back-to-Back Enable (FB2B)
This bit controls whether or not the
master can do fast back-to-back write.
Since device 0 is strictly a target this bit
is not implemented and is hardwired to 0.
Writes to this bit position have no effect.
SERR Enable (SERRE)
SERR messaging. The processor does not
have an SERR signal. The processor
communicates the SERR condition by
sending an SERR message over DMI to
the chipset.
1:The processor is enabled to generate
SERR messages over DMI for specific
Device 0 error conditions that are
individually enabled in the ERRCMD and
DMIUEMSK registers. The error status is
reported in the ERRSTS, PCISTS, and
DMIUEST registers.
0:The SERR message is not generated by
the processor for Device 0.
NOTE: This bit only controls SERR
Address/Data Stepping Enable
(ADSTEP)
Address/data stepping is not
implemented in the processor, and this
bit is hardwired to 0. Writes to this bit
position have no effect.
This bit is a global enable bit for Device 0
Processor Configuration Registers
messaging for the Device 0. The
control bits are used in a logical
OR manner to enable the SERR
DMI message mechanism.
Description
Datasheet