MCP3905L-I/SS Microchip Technology, MCP3905L-I/SS Datasheet - Page 12

• Manufacturer Part Number: MCP3905L-I/SS
• Description: IC,Power Metering,SSOP,24PIN,PLASTIC
• Manufacturer: Microchip Technology

Specifications of MCP3905L-I/SS

• Input Impedance: 390 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.85V
• Current - Supply: 2.7mA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SSOP (0.200", 5.30mm Width)
• Meter Type: Single Phase
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Supply Voltage Range: 4.5V To 5.5V
• Digital Ic Case Style: SSOP
• No. Of Pins: 24
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MCP3905RD-PM1 - REFERENCE DESIGN FOR MCP3905MCP3905EV - BOARD DEMO FOR MCP3905
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MCP3905/06
3.4
CH0- and CH0+ are the fully differential analog voltage
input channels for the current measurement, containing
a PGA for small-signal input, such as shunt current-
sensing. The linear and specified region of this channel
is dependant on the PGA gain. This corresponds to a
maximum differential voltage of ±470 mV/GAIN and
maximum absolute voltage, with respect to A
±1V. Up to ±6V can be applied to these pins without the
risk of permanent damage.
Refer to Section 1.0 “Electrical Characteristics”.
3.5
CH1- and CH1+ are the fully differential analog voltage
input channels for the voltage measurement. The linear
and specified region of these channels have a
maximum differential voltage of ±660 mV and a
maximum absolute voltage of ±1V, with respect to
A
the risk of permanent damage.
Refer to Section 1.0 “Electrical Characteristics”.
3.6
MCLR controls the reset for both delta-sigma ADCs, all
digital registers, the SINC filters for each channel and
all accumulators post multiplier. A logic ‘0’ resets all
registers and holds both ADCs in a Reset condition.
The charge stored in both ADCs is flushed and their
output is maintained to 0x0000h. The only block
consuming power on the digital power supply during
Reset is the oscillator circuit.
3.7
REFIN/OUT is the output for the internal 2.4V
reference. This reference has a typical temperature
coefficient of 15 ppm/°C and a tolerance of ±2%. In
addition, an external reference can also be used by
applying voltage to this pin within the specified range.
REFIN/OUT requires appropriate bypass capacitors to
A
Refer to Section 5.0 “Applications Information”.
3.8
A
circuitry (ADCs, PGA, band gap reference, POR). To
ensure accuracy and noise cancellation, this pin must
be connected to the same ground as D
with a star connection. If an analog ground plane is
available, it is recommended that this device be tied to
this plane of the Printed Circuit Board (PCB). This
plane should also reference all other analog circuitry in
the system.
DS21948E-page 12
GND
GND
GND
. Up to ±6V can be applied to these pins without
, even when using the internal reference only.
is the ground connection to the internal analog
Current Channel (CH0-, CH0+)
Voltage Channel (CH1-,CH1+)
Master Clear (MCLR)
Reference (REFIN/OUT)
Analog Ground (A
GND
)
GND
, preferably
GND
, of
3.9
F2, F1 and F0 select the high-frequency output and
low-frequency output pin ranges by changing the value
of the constants F
function. F
define the period of the output pulses for the device.
3.10
G1 and G0 select the PGA gain on Channel 0 from
three different values: 1, 8 and 16.
3.11
OSC1 and OSC2 provide the master clock for the
device. A resonant crystal or clock source with a similar
sinusoidal waveform must be placed across these pins
to ensure proper operation. The typical clock frequency
specified is 3.579545 MHz. However, the clock
frequency can be with the range of 1 MHz to 4 MHz
without disturbing measurement error. Appropriate
load capacitance should be connected to these pins for
proper operation.
A full-swing, single-ended clock source may be
connected to OSC1 with proper resistors in series to
ensure no ringing of the clock source due to fast
transient edges.
3.12
NEG detects the phase difference between the two
channels and will go to a logic ‘1’ state when the phase
difference is greater than 90° (i.e., when the measured
active (real) power is negative). The output state is
synchronous with the rising-edge of HF
maintains the logic ‘1’ until the active (real) power
becomes positive again and HF
3.13
D
circuitry (SINC filters, multiplier, HPF, LPF, Digital-to-
Frequency (DTF) converter and oscillator). To ensure
accuracy and noise cancellation, D
connected to the same ground as A
with a star connection. If a digital ground plane is
available, it is recommended that this device be tied to
this plane of the PCB. This plane should also reference
all other digital circuitry in the system.
GND
is the ground connection to the internal digital
Frequency Control Logic Pins
(F2, F1, F0)
Gain Control Logic Pins (G1, G0)
Oscillator (OSC1, OSC2)
Negative Power Output Logic Pin
(NEG)
Ground Connection (D
C
and H
C
FC
and H
are the frequency constants that
© 2009 Microchip Technology Inc.
FC
used in the device transfer
OUT
shows a pulse.
GND
GND
GND
, preferably
)
OUT
must be
and