BD87A28FVM-TR Rohm Semiconductor, BD87A28FVM-TR Datasheet - Page 5

• Manufacturer Part Number: BD87A28FVM-TR
• Description: IC, VOLTAGE DETECTION, MSOP8
• Manufacturer: Rohm Semiconductor
• Series: -r
• Type: Watchdog Circuitr

Specifications of BD87A28FVM-TR

• Threshold Voltage: 2.8V
• No. Of Supervisors / Monitors: 1
• Supply Voltage Range: 1V To 10V
• Reset Type: Active-Low
• Supply Current: 5µA
• Digital Ic Case Style: MSOP
• No. Of Pins: 8
• Operating Temperature: RoHS Compliant
• Number Of Voltages Monitored: 1
• Output: Open Drain or Open Collector
• Reset: Active Low
• Reset Timeout: Adjustable/Selectable
• Voltage - Threshold: 2.8V
• Mounting Type: Surface Mount
• Package / Case: 8-VSSOP, 8-MSOP (0.110", 2.80mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

●I/O Circuit diagram
●Timing chart
●Explanation
(1) The RESET pin voltage (RESET) switches to low when the power supply voltage (VDD) falls to 0.8 V.
(2) The external capacitor connected to the CT pin begins to charge when VDD rises above the reset detection voltage (VDETH). The
(3) The external capacitor connected to the CTW pin begins to charge when RESET rises, triggering the watchdog timer.
(4) The CTW pin state switches from charge to discharge when the CTW pin voltage (VCTW) reaches VthH, and RESET switches from high
RESET signal stays low until VDD reaches the VDETH voltage and switches to high when VDD reaches or exceeds the VDETH voltage.
The RESET transmission delay time TPLH allowed to elapse before RESET switches from low to high is given by the following equation:
Rrst denotes the IC's built-in resistance and is designed to be 10 MΩ (Typ.). CT denotes the external capacitor connected to the CT pin.
to low. The watchdog timer monitor time TWH is given by the following equation:
ICTWC denotes the CTW charge current and is designed to be 0.50 µA (Typ.). CTW denotes the external capacitor connected to the
CTW pin.
(BD37A□□FVM／BD99A41F)
CTW
CLK
TPLH (s) ≈ 0.69 × Rrst × CT (µF)
TWH (s) ≈ (0.5 × CTW (µF))/(ICTWC)
VDD
(BD87A□□FVM)
VDD
CTW
CT
VDD
VCTW
CLK
VCT VCTH
INH
INH
VDD
RESET
0
0
0
0
0
0
VDETH
0
VDET
VthH
VthL
(1) (2) (3)
TPLH
*1
[1]
(4) (5)
TWH
*2
[2]
(4)
*4 TWCLK
(5)
INH
TWL
*3
(6)
(7)
TWCLK
(7)
VDD
Fig.15
Fig.16
5/8
RESET
(4) (5) (8)
INH
WDT circuit turns off
when INH is low.
(9)
WDT circuit turns off
when INH is high.
(4)
RESET
(5)
(10)
(2)
(3)
(4) (5) (10) (2)
CT
(3)
VDD
(4) (5)
(10)
(11)
VDETH = VDET + Vrhys
VDD
CT
10MΩ(Typ.)