AD669BR Analog Devices Inc, AD669BR Datasheet - Page 10

• Manufacturer Part Number: AD669BR
• Description: IC,D/A CONVERTER,SINGLE,16-BIT,BICMOS,SOP,28PIN
• Manufacturer: Analog Devices Inc
• Series: DACPORT®r

Specifications of AD669BR

• Rohs Compliant: NO
• Rohs Status: RoHS non-compliant
• Settling Time: 10µs
• Number Of Bits: 16
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Dual ±
• Power Dissipation (max): 625mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Converter Type: DAC
• Current, Output: 5 mA (Min.)
• Number Of Pins: 28
• Package Type: SOIC
• Power Dissipation: 365 mW (Typ.)
• Resolution: 16 Bits (Min.)
• Temperature, Operating, Maximum: 85 °C
• Temperature, Operating, Minimum: -40 °C
• Voltage, Input, High Level: 2 V (Min.)
• Voltage, Input, Low Level: 0 to 0.8 V
• Voltage, Output: 0 to +10 V (Unipolar), -10 to +10 V (Bipolar)
• Voltage, Range: +13.5 to +16.5 V
• Resolution (bits): 16bit
• Sampling Rate: 167kSPS
• Input Channel Type: Parallel
• Supply Voltage Range - Analog: 13.5V To 16.5V
• Supply Current: 12mA
• Digital Ic Case Style: SOIC

AD669
tied together which configures the input stage as an edge trig-
gered 16-bit register. The rising edge of the decoded signal
latches the data and updates the output of the DAC. It is neces-
sary to insert wait states after the processor initiates the write
cycle to comply with the timing requirements t
Figure 1b. The number of wait states that are required will vary
depending on the processor cycle time. The equation given in
Figure 9 can be used to determine the number of wait states
given the frequency of the processor crystal.
As an example, the 20.48 MHz crystal used in this application
results in T = 24.4 ns which means that the required number of
wait states is about 2.76. This must be rounded to the next
highest integer to assure that the minimum pulse widths comply
with those required by the AD669. As the speed of the proces-
sor is increased, the data hold time relative to CS1 decreases. As
processor clocks increase beyond 20.48 MHz, a configuration
such as the one shown for the ADSP-2101 is the better choice.
AD669 TO 8086 INTERFACE
Figure 10 shows the 8086 16-bit microprocessor connected to
multiple AD669s. The double-buffered capability of the AD669
allows the microprocessor to write to each AD669 individually
and then update all the outputs simultaneously. Processor
speeds of 6, 8, and 10 MHz require no wait states to interface
with the AD669.
The 8086 software routine begins by writing a data word to the
CS1 address. The decoder must latch the address using the
ALE signal. The decoded CS1 pulse goes low causing the first
rank latch of the associated AD669 to become transparent.
Simultaneously, the 8086 places data on the multiplexed bus
which is then latched into the first rank of the AD669 with the
rising edge of the WR pulse. Care should be taken to prevent
excessive delays through the decoder potentially resulting in a
violation of the AD669 data hold time (t
XTAL
Figure 9. DSP56001 to AD669 Interface
DSP56001
DGND
+5V
V
A0–A15
D0–D23
LL
IRQA
X/Y
WR
DS
T =
WAIT STATES =
# OF
2 (XTAL)
EXTERNAL
ADDRESS
DECODE
CLOCK
1
74F32
t
LOW
DH
DB0–DB15
– T + 9ns
).
CS1
2T
LOW
CS
L1
LDAC
shown in
AD669
V
LL
DGND
–10–
The same procedure is repeated until all three AD669s have had
their first rank latches loaded with the desired data. A final write
command to the LDAC address results in a high-going pulse
that causes the second rank latches of all the AD669s to become
transparent. The falling edge of LDAC latches the data from the
first rank until the next update. This scheme is easily expanded
to include as many AD669s as required.
8-BIT MICROPROCESSOR INTERFACE
The AD669 can easily be operated with an 8-bit bus by the ad-
dition of an octal latch. The 16-bit first rank register is loaded
from the 8-bit bus as two bytes. Figure 11 shows the configura-
tion when using a 74HC573 octal latch.
The eight most significant bits are latched into the 74HC573 by
setting the “latch enable” control line low. The eight least sig-
nificant bits are then placed onto the bus. Now all sixteen bits
can be simultaneously loaded into the first rank register of the
AD669 by setting CS and L1 low.
AD0 – AD15
8086
DGND
+5V
V
Figure 11. Connections for 8-Bit Bus Interface
CONTROL
LL
8-BIT P
M/I0
ALE
AND
WR
Figure 10. 8086-to-AD669 Interface
D7
D0
LDAC CS1 CS2 CS3
ADDRESS
DECODE
D7
D0
74HC573
11
Q0
Q7
CS
CS
LDAC
CS
LDAC
LDAC
DB0 – DB15
DB0 – DB15
DB0 – DB15
MSB
LSB
DB8
DB7
CS1 L1
AD669
AD669
AD669
DGND L1
DGND L1
DGND L1
AD669
LDAC
V
V
V
V
V
V
LL
LL
LL
OUT
OUT
OUT
REV. A