AD669BR Analog Devices Inc, AD669BR Datasheet - Page 9

• Manufacturer Part Number: AD669BR
• Description: IC,D/A CONVERTER,SINGLE,16-BIT,BICMOS,SOP,28PIN
• Manufacturer: Analog Devices Inc
• Series: DACPORT®r

Specifications of AD669BR

• Rohs Compliant: NO
• Rohs Status: RoHS non-compliant
• Settling Time: 10µs
• Number Of Bits: 16
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Dual ±
• Power Dissipation (max): 625mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Converter Type: DAC
• Current, Output: 5 mA (Min.)
• Number Of Pins: 28
• Package Type: SOIC
• Power Dissipation: 365 mW (Typ.)
• Resolution: 16 Bits (Min.)
• Temperature, Operating, Maximum: 85 °C
• Temperature, Operating, Minimum: -40 °C
• Voltage, Input, High Level: 2 V (Min.)
• Voltage, Input, Low Level: 0 to 0.8 V
• Voltage, Output: 0 to +10 V (Unipolar), -10 to +10 V (Bipolar)
• Voltage, Range: +13.5 to +16.5 V
• Resolution (bits): 16bit
• Sampling Rate: 167kSPS
• Input Channel Type: Parallel
• Supply Voltage Range - Analog: 13.5V To 16.5V
• Supply Current: 12mA
• Digital Ic Case Style: SOIC

REV. A
Unipolar coding is straight binary, where all zeros (0000H) on
the data inputs yields a zero analog output and all ones
(FFFFH) yields an analog output 1 LSB below full scale.
Bipolar coding is offset binary, where an input code of 0000H
yields a minus full-scale output, an input of FFFFH yields an
output 1 LSB below positive full scale, and zero occurs for an
input code with only the MSB on (8000H).
The AD669 can be used with twos complement input coding if
an inverter is used on the MSB (DB15).
DIGITAL INPUT CONSIDERATIONS
The threshold of the digital input circuitry is set at 1.4 volts.
The input lines can thus interface with any type of 5 volt logic.
The AD669 data and control inputs will float to indeterminate
logic states if left open. It is important that CS and L1 be con-
nected to DGND and Chat LDAC be tied to V
are not used.
Fanout for the AD669 is 40 when used with a standard low
power Schottky gate output device.
16-BIT MICROPROCESSOR INTERFACE
The 16-bit parallel registers of the AD669 allow direct interfac-
ing to 16-bit general purpose and DSP microprocessor buses.
The following examples illustrate typical AD669 interface
configurations.
AD669 TO ADSP-2101 INTERFACE
The flexible interface of the AD669 minimizes the required
“glue” logic when it is connected in configurations such as the
one shown in Figure 8. The AD669 is mapped into the ADSP-
2101’s memory space and requires two wait states using a 12.5
MHz processor clock.
In this configuration, the ADSP-2101 is set up to use the inter-
nal timer to interrupt the processor at the desired sample rate.
The WR pin and data lines D8–D23 from the ADSP-2101 are
tied directly to the L1 and DB0 through DB15 pins of the
AD669, respectively. The decoded signal CS1 is connected to
both CS and LDAC. When a timer interrupt is detected, the
ADSP-2101 automatically vectors to the appropriate service
routine with minimal overhead. The interrupt routine then in-
structs the processor to execute a data memory write to the ad-
dress of the AD669.
The WR pin and CS1 both go low causing the first 16-bit latch
inside the AD669 to be transparent. The data present in the first
rank is then latched by the rising edge of WR. The rising edge
of CS1 will cause the second rank 16-bit latch to become
transparent updating the output of the DAC. The length of
WR is extended by two wait states to comply with the timing
requirements of t
latch the data with the rising edge of WR rather than the decoded
CS1. This is necessary to comply with the t
the AD669.
LOW
shown in Figure 1b. It is important to
DH
specification of
LL
if these pins
–9–
Figure 8b shows the circuitry a typical decoder might include.
In this case, a data memory write to any address in the range
3000H to 3400H will result in the AD669 being updated. These
decoders will vary greatly depending on the number of devices
memory-mapped by the processor.
AD669 TO DSP56001 INTERFACE
Figure 9 shows the interface between the AD669 and the
DSP56001. Like the ADSP-2101, the AD669 is mapped into
the DSP56001’s memory space. This application was tested
with a processor clock of 20.48 MHz (t
faster rates are possible.
An external clock connected to the IRQA pin of the DSP56001
interrupts the processor at the desired sample rate. If ac perfor-
mance is important, this clock should be synchronous with the
DSP56001 processor clock. Asynchronous clocks will cause jit-
ter on the latch signal due to the uncertainty associated with the
acknowledgment of the interrupt. A synchronous clock is easily
generated by dividing down the clock from the DSP crystal. If
ac performance is not important, it is not necessary for IRQA to
be synchronous.
After the interrupt is acknowledged, the interrupt routine ini-
tiates a memory write cycle. All of the AD669 control inputs are
ADSP-2101
Figure 8. ADSP-2101 to AD669 Interface
DGND
+5V
V
LL
DMS
A13
A12
A11
a. ADSP-2101 to AD669 Interface
DMS
A13
WR
D23
A0
D8
b. Typical Address Decoder
ADDRESS BUS
DECODER
DATA BUS
CS1
L1
LDAC
CS
CYC
DB0
AD669
= 97.66 ns) although
V
DB15
LL
AD669
CS1
DGND
V
OUT