AD7719BRUZ Analog Devices Inc, AD7719BRUZ Datasheet - Page 22

• Manufacturer Part Number: AD7719BRUZ
• Description: Dual 16-Bit & 24-Bit SD ADC
• Manufacturer: Analog Devices Inc

Specifications of AD7719BRUZ

• Number Of Bits: 16/24
• Sampling Rate (per Second): 105
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 4.5mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP (0.173", 4.40mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7719EB - BOARD EVAL FOR AD7719
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD7719
Operating Characteristics when Addressing the Mode and
Control Registers
1. Any change to the MD bits will immediately reset both ADCs.
2. If AD0CON is written when AD0EN = 1, or if AD0EN is
3. On the other hand, if AD1CON is written to, only the aux
4. Once the MODE has been written with a calibration mode,
Bit Location
AD0CON7
AD0CON6
AD0CON5
AD0CON4
CHCON
0
0
0
0
1
1
1
1
AD0CON3
A write to the MD2–0 bits with no change is also treated as a
reset. (See exception to this in Note 3.)
changed from 0 to 1, both ADCs are also immediately reset. In
other words, the main ADC is given priority over the aux ADC
and any change requested on main is immediately responded to.
ADC is reset. For example, if the main ADC is continuously
converting when the aux ADC change or enable occurs, the
main ADC continues undisturbed. Rather than allow the aux
ADC to operate with a phase difference from the main ADC,
the aux ADC will fall into step with the outputs of the main
ADC. The result is that the first conversion time for the aux
channel will be delayed up to three outputs while the aux ADC
update rate is synchronized to the main ADC.
the RDY0/1 bits (STATUS) are immediately reset and the
A
A
D
D
0
0
E
C
N
O
N
(
) 0
7
Bit Name
AD0EN
WL
CH1
CH0
CH1
0
0
1
1
0
0
1
1
U/B
A
D
W
0
L
C
(
O
) 0
Table XIII. Main ADC Control Register (AD0CON) Bit Designations
N
Description
Main ADC Enable Bit.
Set by user to enable the main ADC. When set, the main ADC operates according to the MD bits in
the mode register.
Cleared by the user to power down the Main ADC.
16-/24-Bit Operating Mode.
Set by user to enable 16-bit mode. The conversion results from the main ADC will be rounded to
16 bits and the main ADC data register will be 16 bits wide.
Cleared by user to enable 24-bit mode. The conversion results from the main ADC will be rounded to
24 bits and the main ADC data register will be 24 bits wide.
Main ADC Channel Selection Bits.
Written by the user to select the differential input pairs used by the main ADC as follows:
(Note: The CHCON bit resides in the Mode register.)
CH0
0
1
0
1
0
1
0
1
Main ADC Unipolar/Bipolar Bit.
Set by user to enable unipolar coding, i.e., zero differential input will result in 0x00 0000 output and
a full-scale differential input will result in 0xFF FFFF output when operated in 24-bit mode.
Cleared by user to enable bipolar coding, Negative full-scale differential input will result in an output
code of 0x00 0000, zero differential input will result in an output code of 0x80 0000, and a
Positive full-scale differential input will result in an output code of 0xFF FFFF.
6
A
C
D
H
0
C
1
Positive Input
AIN1
AIN3
AIN2
AIN3
AIN1
AIN3
AIN4
AIN2
O
(
) 0
N
5
A
C
D
H
0
C
0
O
(
) 0
N
4
–22–
Negative Input
AIN2
AIN4
AIN2
AIN2
AIN4
AIN4
AIN4
AIN4
A
5. Any calibration request of the aux ADC while the temperature
6. Calibrations are performed with the maximum allowable SF
Main ADC Control Register (AD0CON): (A3, A2, A1, A0 = 0,
0, 1, 0; Power-On Reset = 0x07)
The main ADC control register is an 8-bit register from which data
can be read or to which data can be written. This register is used to
configure the main ADC for range, channel selection, 16-/24-bit
operation, and unipolar or bipolar coding. Table XIII outlines
the bit designations for the main ADC control register. AD0CON7
through AD0CON0 indicate the bit location, AD0CON denoting
the bits are in the main ADC control register. AD0CON7 denotes
the first bit of the data stream. The number in parentheses
indicates the power-on/reset default status of that bit.
D
U B
calibration commences. On completion, the appropriate calibra-
tion registers are written, the relevant bits in STATUS are
written, and the MD2–0 bits are reset to 001 to indicate the
ADC is back in Idle mode.
sensor is selected will fail to complete.
value. SF register is reset to user configuration after calibration.
/
0
C
O
(
) 0
N
3
A
R
D
N
0
Calibration Register Pair
0
1
0
1
0
1
0
2
C
2
O
(
) 1
N
2
A
R
D
N
0
C
1
O
(
) 1
N
1
A
R
D
N
0
C
0
O
(
) 1
N
REV. A
0