AD7719BRUZ Analog Devices Inc, AD7719BRUZ Datasheet - Page 7

• Manufacturer Part Number: AD7719BRUZ
• Description: Dual 16-Bit & 24-Bit SD ADC
• Manufacturer: Analog Devices Inc

Specifications of AD7719BRUZ

• Number Of Bits: 16/24
• Sampling Rate (per Second): 105
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 4.5mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP (0.173", 4.40mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7719EB - BOARD EVAL FOR AD7719
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TIMING CHARACTERISTICS
AGND = DGND = 0 V; X
Parameter
t
t
Read Operation
Write Operation
NOTES
1
2
3
4
5
6
7
Specifications subject to change without notice.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7719 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. A
1
2
Sample tested during initial release to ensure compliance. All input signals are specified with t
See Figures 2 and 3.
SCLK active edge is falling edge of SCLK.
These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V
This specification only comes into play if CS goes low while SCLK is low. It is required primarily for interfacing to DSP machines.
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the Timing Characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
RDY returns high after a read of both ADCs. The same data can be read again, if required, while RDY is high, although care should be taken that subsequent reads
do not occur close to the next output update.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
3
4
5
5A
6
7
8
9
10
11
12
13
14
15
16
4
6
4, 5
TAL
= 32.768 kHz; Input Logic 0 = 0 V, Logic 1 = DV
Limit at T
(B Version)
32.768
50
0
0
0
60
80
0
60
80
100
100
0
10
80
100
0
30
25
100
100
0
MIN
Figure 1. Load Circuit for Timing Characterization
1, 2
, T
(AV
TO OUTPUT
MAX
DD
PIN
= 2.7 V to 3.6 V or AV
50pF
Unit
kHz typ
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns min
I
I
SINK
SOURCE
–7–
100 A WITH DV
(1.6mA WITH DV
DD
DD
, unless otherwise noted.)
(200 A WITH DV
100 A WITH DV
= 4.75 V to 5.25 V; DV
R
= t
1.6V
F
= 5 ns (10% to 90% of DV
Conditions/Comments
Crystal Oscillator Frequency
RESET Pulsewidth
RDY to CS Setup Time
CS Falling Edge to SCLK Active Edge Setup Time
SCLK Active Edge to Data Valid Delay
DV
DV
CS Falling Edge to Data Valid Delay
DV
DV
SCLK High Pulsewidth
SCLK Low Pulsewidth
CS Rising Edge to SCLK Inactive Edge Hold Time
Bus Relinquish Time after SCLK Inactive Edge
SCLK Active Edge to RDY High
CS Falling Edge to SCLK Active Edge Setup Time
Data Valid to SCLK Edge Setup Time
Data Valid to SCLK Edge Hold Time
SCLK High Pulsewidth
SCLK Low Pulsewidth
CS Rising Edge to SCLK Edge Hold Time
DD
DD
= 3V)
DD
DD
DD
DD
= 5V
DD
DD
= 3V)
= 5V
= 4.75 V to 5.25 V
= 2.7 V to 3.6 V
= 4.75 V to 5.25 V
= 2.7 V to 3.6 V
DD
= 2.7 V to 3.6 V or DV
DD
OL
) and timed from a voltage level of 1.6 V.
or V
WARNING!
OH
limits.
3, 7
DD
ESD SENSITIVE DEVICE
= 4.75 V to 5.25 V;
3
3
AD7719
3
3
3
3