CDB4364 Cirrus Logic Inc, CDB4364 Datasheet
CDB4364
Specifications of CDB4364
Related parts for CDB4364
CDB4364 Summary of contents
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D/A Converter Features Advanced Multi-bit Delta Sigma Architecture 24-bit Conversion Automatic Detection of Sample Rates up to 192 kHz 103 dB Dynamic Range -88 dB THD+N Single-Ended Output Architecture ® Direct Stream Digital (DSD – ...
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TABLE OF CONTENTS 1. PIN DESCRIPTION................................................................................................................................. 6 2. CHARACTERISTICS AND SPECIFICATIONS...................................................................................... 8 RECOMMENDED OPERATING CONDITIONS .......................................................................................... 8 ABSOLUTE MAXIMUM RATINGS............................................................................................................... 8 DAC ANALOG CHARACTERISTICS........................................................................................................... 9 POWER AND THERMAL CHARACTERISTICS........................................................................................ 10 COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE............................................ 11 COMBINED INTERPOLATION ...
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PCM Control (Address 03h) .......................................................................................................... 34 6.3.1 Digital Interface Format (DIF)............................................................................................... 34 6.3.2 Functional Mode (FM) .......................................................................................................... 35 6.4 DSD Control (Address 04h) ........................................................................................................... 35 6.4.1 DSD Mode Digital Interface Format (DSD_DIF) .................................................................. 35 6.4.2 Direct DSD Conversion (DIR_DSD)..................................................................................... ...
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LIST OF FIGURES Figure 1. Serial Audio Interface Timing...................................................................................................... 14 Figure 2. Direct Stream Digital - Serial Audio Input Timing........................................................................ 15 Figure 3. Direct Stream Digital - Serial Audio Input Timing for Phase Modulation Mode........................... 15 Figure 4. Control Port ...
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LIST OF TABLES Table 1. Single-Speed Mode Standard Frequencies ................................................................................ 20 Table 2. Double-Speed Mode Standard Frequencies............................................................................... 20 Table 3. Quad-Speed Mode Standard Frequencies ................................................................................. 20 Table 4. PCM Digital Interface Format, Hardware Mode Options............................................................. 21 Table 5. Mode Selection, ...
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PIN DESCRIPTION M4(TST) M3(TST) Pin Name # Digital Power (Input) - Positive power supply for the digital section. Refer to the Recommended VD 4 Operating Conditions for appropriate voltages. 5 GND Ground (Input) - Ground reference. Should be connected ...
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Pin Name # Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling cir- FILT+ 20 cuits. Requires the capacitive decoupling to analog ground as shown in the Typical Connection Diagram. AOUT1 39 AOUT2 38 AOUT3 35 Analog ...
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CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS (GND = 0 V; all voltages with respect to ground.) Parameters DC Power Supply Ambient Operating Temperature (Power Applied) ABSOLUTE MAXIMUM RATINGS (GND = 0 V; all voltages with respect to ground.) Parameters ...
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DAC ANALOG CHARACTERISTICS Test Conditions (unless otherwise indicated VLS = VLC = 2 input sine wave ; Tested under max ac-load resistance; Valid with FILT+ and VQ capacitors as shown ...
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POWER AND THERMAL CHARACTERISTICS Parameters Power Supplies Power Supply Current (Note 4) (Note 5) (Note 6) Power Dissipation (Note 4) Package Thermal Resistance Power Supply Rejection Ratio (Note 7) Notes: 4. Current consumption increases with increasing FS within a given ...
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COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sam- ple rate by multiplying the given characteristic by Fs. (See ) (Note 12) Parameter ...
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COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (CONTINED) Parameter Single-Speed Mode - 48 kHz Passband (Note 9) Frequency Response StopBand StopBand Attenuation Group Delay De-emphasis Error (Note 11) (Relative to 1 kHz) Double-Speed Mode - 96 kHz Passband (Note 9) ...
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DIGITAL CHARACTERISTICS Parameters Input Leakage Current Input Capacitance High-Level Input Voltage Low-Level Input Voltage Low-Level Output Voltage (I = -1.2 mA) OL MUTEC auto detect input high voltage MUTEC auto detect input low voltage Maximum MUTEC Drive Current MUTEC High-Level ...
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SWITCHING CHARACTERISTICS - PCM (Inputs: Logic 0 = GND, Logic 1 = VLS, C Parameters RST pin Low Pulse Width MCLK Frequency MCLK Duty Cycle Input Sample Rate - LRCK (Manual selection) Input Sample Rate - LRCK (Auto detect) LRCK ...
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SWITCHING CHARACTERISTICS - DSD (Logic 0 = AGND = DGND; Logic 1 = VLS; C Parameter MCLK Duty Cycle DSD_SCLK Pulse Width Low DSD_SCLK Pulse Width High DSD_SCLK Frequency DSD_A / _B valid to DSD_SCLK rising setup time DSD_SCLK rising ...
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SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT (Inputs: Logic 0 = GND, Logic 1 = VLC, C Parameter SCL Clock Frequency RST Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock ...
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SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT (Inputs: Logic 0 = GND, Logic 1 = VLC, C Parameter CCLK Clock Frequency RST Rising Edge to CS Falling CCLK Edge to CS Falling CS High Time Between Transmissions CS Falling ...
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TYPICAL CONNECTION DIAGRAM +2.5 V PCM Digital Audio Source +1 DSD Audio Source Micro- Controller +1 Note*: Necessary for Figure 6. Typical Connection Diagram, Software Mode µF 0.1 ...
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V PCM Digital Audio Source +1 DSD Audio Source Stand-Alone Mode Configuration +1 Figure 7. Typical Connection Diagram, Hardware Mode DS619F1 + 1 µF 0.1 µ ...
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APPLICATIONS The CS4364 serially accepts twos complement formatted PCM data at standard audio sample rates including 48, 44.1 and 32 kHz in SSM, 96, 88.2 and 64 kHz in DSM, and 192, 176.4 and 128 kHz in QSM. Audio ...
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Mode Select In Hardware Mode, operation is determined by the Mode Select pins. The states of these pins are continu- ally scanned for any changes; however, the mode should only be changed while the device is in reset (RST ...
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Digital Interface Formats The serial port operates as a slave and supports the I²S, Left-Justified, Right-Justified, and One-Line Mode (OLM) digital interface formats with varying bit depths from shown in clocked into the DAC on ...
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LRCK Left Channel SCLK SDINx clocks 4.3.1 OLM #1 OLM #1 serial audio interface format operates in Single-, Double-, or Quad-Speed Mode and will slave to SCLK at 128 ...
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Interpolation Filter To accommodate the increasingly complex requirements of digital audio systems, the CS4364 incorporates selectable interpolation filters for each mode of operation. A “fast” and a “slow” roll-off filter is available in each of Single-, Double-, or Quad-Speed ...
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ATAPI Specification The implements the channel mixing functions of the ATAPI CD-ROM specification. The CS4364 ATAPI functions are applied per A-B pair. Refer to tion. Left Chan nel Audio D ata SDINx Right Chan nel Audio D ata Figure ...
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... Note: All decoupling capacitors should be referenced to analog ground. The CDB4364 evaluation board demonstrates the optimum layout and power supply arrangements. 4.10 Analog Output and Filtering The CS4364 does not include phase or amplitude compensation for an external filter. Therefore, the DAC system phase and amplitude response will be dependent on the external analog circuitry ...
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AOUT Full-Scale Output Level= AOUT= 3.35 Vpp 4.11 The MUTEC Outputs The MUTEC1 pins have an auto-polarity detect feature. The MUTEC output pins are high impedance at the time of reset. The external mute circuitry needs to be self biased ...
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Recommended Power-Up Sequence 4.12.1 Hardware Mode 1. Hold RST low until the power supplies and configuration pins are stable, and the master and left/right clocks are locked to the appropriate frequencies, as discussed in registers are reset to the ...
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Hardware Mode settings). 4. Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately 50 µs. 4.13 Recommended Procedure for Switching Operational Modes For systems where the absolute minimum in clicks ...
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I²C Read To read from the device, follow the procedure below while adhering to the control port Switching Specifica- tions. 1. Initiate a START condition to the 001100. The seventh bit must match the setting of the AD0 pin, ...
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If the INCR bit is set to 0 and further SPI writes to other registers are desired necessary to bring CS high, and follow the procedure detailed from step further writes to other registers ...
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REGISTER QUICK REFERENCE Addr Function 7 01h Chip Revision PART4 default 0 02h Mode Control CPEN default 0 03h PCM Control DIF3 default 0 04h DSD Control DSD_DIF2 DSD_DIF1 DSD_DIF0 DIR_DSD STATIC_D default 0 05h Filter Control Reserved default ...
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REGISTER DESCRIPTION Note: All registers are read/write in I²C Mode and write only in SPI, unless otherwise noted. 6.1 Chip Revision (Address 01h PART4 PART3 PART2 0 1 6.1.1 Part Number ID (PART) [Read Only] 01100 - ...
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PCM/DSD Selection (DSD/PCM) Default = PCM 1 - DSD Function: This function selects DSD or PCM Mode. The appropriate data and clocks should be present before changing modes, or else MUTE should be selected. 6.2.4 DAC ...
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DIF3 DIF2 DIF1 DIF0 ...
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Direct DSD Conversion (DIR_DSD) Function: When set to 0 (default), DSD input data is sent to the DSD processor for filtering and volume control func- tions. When set to 1, DSD input data is sent directly to the switched ...
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Filter Control (Address 05h Reserved Reserved Reserved 0 0 6.5.1 Interpolation Filter Select (FILT_SEL) Function: When set to 0 (default), the Interpolation Filter has a fast roll off. When set to 1, the Interpolation Filter has a ...
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Function: The AOUTAx and AOUTBx volume levels are independently controlled by the A and the B Channel Vol- ume Control Bytes when this function is disabled. The volume on both AOUTAx and AOUTBx are deter- mined by the A Channel ...
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The zero cross function is independently monitored and implemented for each channel. 6.8.2 Soft Volume Ramp-Up After Error (RMP_UP) Function: An un-mute will be performed after executing an LRCK/MCLK ...
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MUTE Polarity and DETECT (MUTEP1:0) Default = Auto polarity detect, selected from MUTEC1 pin 01 - Reserved 10 - Active low mute polarity 11 - Active high mute polarity Function: Auto mute polarity detect (00) See ...
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Selects the appropriate digital filter to maintain the standard 15 µs/50 µs digital de-emphasis filter re- sponse at 32, 44 kHz sample rates. De-emphasis is only available in Single-Speed Mode. 6.10.2 ATAPI Channel Mixing and Muting (ATAPI) Default ...
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Volume Control (Address 0Bh, 0Ch, 0Eh, 0Fh, 11h, 12h xx_VOL7 xx_VOL6 xx_VOL5 0 0 These six registers provide individual volume and mute control for each of the six channels. The values for “xx” in the bit fields ...
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FILTER RESPONSE PLOTS 0 −20 −40 −60 −80 −100 −120 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) Figure 24. Single-Speed (fast) Stopband Rejection 0 −1 −2 −3 −4 −5 −6 −7 −8 −9 −10 0.45 0.46 0.47 0.48 0.49 ...
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Frequency(normalized to Fs) Figure 30. Single-Speed (slow) Transition Band (detail 100 120 0.4 0.5 0.6 0.7 Frequency(normalized ...
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Frequency(normalized to Fs) Figure 36. Double-Speed (slow) Stopband Rejection 0.45 0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized ...
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Frequency(normalized to Fs) Figure 42. Quad-Speed (fast) Transition Band (detail 100 120 0.1 0.2 0.3 0.4 0.5 ...
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... How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters, by Steven Harris. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992. 2. CDB4364 data sheet, available at http://www.cirrus.com. 3. Design Notes for a 2-Pole Filter with Differential Input, by Steven Green. Cirrus Logic Application Note AN48 4 ...
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DIMENSIONS 48L LQFP PACKAGE DRAWING D1 D DIM MIN A --- A1 0.002 B 0.007 D 0.343 D1 0.272 E 0.343 E1 0.272 e* 0.016 L 0.018 ∝ 0.000° ∝ L INCHES NOM ...
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... INFORMATION Product Description 114 dB, 192 kHz 6- CS4364 channel D/A Converter CDB4364 CS4364 Evaluation Board DS619F1 Package Pb-Free Grade Temp Range 48-pin YES Commercial -40° to +85° C LQFP - - CS4364 Container Order # Tray CS4364-CQZ Tape & Reel CS4364-CQZR - - CDB4364 49 ...
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HISTORY Release A1 Initial Release Corrected DAC Pair Disable register description in Added note to Digital Interface Format register description in Removed TDM Mode functionality Removed Automotive Grade Added PCM mode format changeable in reset only to F1 Updated ...