CS42L51-DNZ Cirrus Logic Inc, CS42L51-DNZ Datasheet - Page 5

• Manufacturer Part Number: CS42L51-DNZ
• Description: Automotive Portable Stereo Codec
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS42L51-DNZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 98 / 98
• Voltage - Supply, Analog: 1.8V, 2.5V
• Voltage - Supply, Digital: 1.8V, 2.5V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1005 - BOARD EVAL FOR CS42L51 CODEC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1627

CS42L51
11. PARAMETER DEFINITIONS .............................................................................................................. 83
12. PACKAGE DIMENSIONS ................................................................................................................. 84
THERMAL CHARACTERISTICS ........................................................................................................ 84
13. ORDERING INFORMATION ............................................................................................................. 85
14. REFERENCES .................................................................................................................................... 85
15. REVISION HISTORY ......................................................................................................................... 86
LIST OF FIGURES
Figure 1.Typical Connection Diagram (Software Mode) ........................................................................... 10
Figure 2.Typical Connection Diagram (Hardware Mode) .......................................................................... 11
Figure 3.Headphone Output Test Load ..................................................................................................... 19
Figure 4.Serial Audio Interface Slave Mode Timing .................................................................................. 21
Figure 5.Serial Audio Interface Master Mode Timing ................................................................................ 21
Figure 6.Control Port Timing - I²C ............................................................................................................. 22
Figure 7.Control Port Timing - SPI Format ................................................................................................ 23
Figure 8.Analog Input Architecture ............................................................................................................ 28
Figure 9.MIC Input Mix w/Common Mode Rejection ................................................................................. 30
Figure 10.Differential Input ........................................................................................................................ 30
Figure 11.ALC ........................................................................................................................................... 32
Figure 12.Noise Gate Attenuation ............................................................................................................. 33
Figure 13.Output Architecture ................................................................................................................... 34
Figure 14.De-Emphasis Curve .................................................................................................................. 35
Figure 15.Beep Configuration Options ...................................................................................................... 36
Figure 16.Peak Detect & Limiter ............................................................................................................... 37
Figure 17.Master Mode Timing ................................................................................................................. 39
Figure 18.Tri-State Serial Port .................................................................................................................. 40
Figure 19.I²S Format ................................................................................................................................. 40
Figure 20.Left-Justified Format ................................................................................................................. 41
Figure 21.Right-Justified Format (DAC only) ............................................................................................ 41
Figure 22.Initialization Flowchart ............................................................................................................... 42
Figure 23.Control Port Timing in SPI Mode .............................................................................................. 43
Figure 24.Control Port Timing, I²C Write ................................................................................................... 44
Figure 25.Control Port Timing, I²C Read ................................................................................................... 44
Figure 26.AIN & PGA Selection ................................................................................................................ 56
Figure 27.THD+N vs. Output Power per Channel at 1.8 V (16 Ω load) .................................................... 75
Figure 28.THD+N vs. Output Power per Channel at 2.5 V (16 Ω load) .................................................... 75
Figure 29.THD+N vs. Output Power per Channel at 1.8 V (32 Ω load) .................................................... 76
Figure 30.THD+N vs. Output Power per Channel at 2.5 V (32 Ω load) .................................................... 76
Figure 31.Power Dissipation vs. Output Power into Stereo 16 Ω ......................................................................77
Figure 32.Power Dissipation vs. Output Power into Stereo 16 Ω (Log Detail) .......................................... 77
Figure 33.ADC THD+N vs. Frequency w/Capacitor Effects ...................................................................... 78
Figure 34.ADC Passband Ripple .............................................................................................................. 82
Figure 35.ADC Stopband Rejection .......................................................................................................... 82
Figure 36.ADC Transition Band ................................................................................................................ 82
Figure 37.ADC Transition Band Detail ...................................................................................................... 82
Figure 38.DAC Passband Ripple .............................................................................................................. 82
Figure 39.DAC Stopband .......................................................................................................................... 82
Figure 40.DAC Transition Band ................................................................................................................ 82
Figure 41.DAC Transition Band (Detail) .................................................................................................... 82
DS679F1
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