CS42L51-DNZ Cirrus Logic Inc, CS42L51-DNZ Datasheet - Page 73

• Manufacturer Part Number: CS42L51-DNZ
• Description: Automotive Portable Stereo Codec
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS42L51-DNZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 98 / 98
• Voltage - Supply, Analog: 1.8V, 2.5V
• Voltage - Supply, Digital: 1.8V, 2.5V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1005 - BOARD EVAL FOR CS42L51 CODEC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1627

CS42L51
Function:
Sets the threshold level of the noise gate. Input signals below the threshold level will be attenuated to -96
dB. NG_BOOST = ‘1’b adds 30 dB to the threshold settings.
Noise Gate Delay Timing (NGDELAY[1:0])
Default: 00
00 - 50 ms
01 - 100 ms
10 - 150 ms
11 - 200 ms
Function:
Sets the delay time before the noise gate attacks. Noise gate attenuation is dictated by the SOFTx &
ZCROSS bit settings unless the disable bit for each function is enabled.
6.27
Status (Address 20h) (Read Only)
7
6
5
4
3
2
1
0
Reserved
SP_CLKERR
SPEA_OVFL
SPEB_OVFL
PCMA_OVFL PCMB_OVFL ADCA_OVFL
ADCB_OVFL
For all bits in this register, a “1” means the associated error condition has occurred at least once since the
register was last read. A ”0” means the associated error condition has NOT occurred since the last reading
of the register. Reading the register resets all bits to 0.
Serial Port Clock Error (SP_CLK Error)
Default: 0
Function:
Indicates an invalid MCLK to LRCK ratio. See
“Serial Port Clocking” on page 38
for valid clock ratios.
Note:
On initial power up and application of clocks, this bit will be high as the serial port re-synchronizes.
Signal Processing Engine Overflow (SPEX_OVFL)
Default: 0
Function:
Indicates a digital overflow condition within the data path after the signal processing engine.
PCMX Overflow (PCMX_OVFL)
Default: 0
Function:
Indicates a digital overflow condition within the data path of the PCM mix.
ADC Overflow (ADCX_OVFL)
Default = 0
Function:
Indicates that there is an over-range condition anywhere in the CS42L51 ADC signal path of each of the
associated ADC’s.
DS679F1
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