CS4397-KS Cirrus Logic Inc, CS4397-KS Datasheet
CS4397-KS
Specifications of CS4397-KS
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CS4397-KS Summary of contents
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... This multi-bit ar- chitecture features significantly lower out-of-band noise and jitter sensitivity than traditional 1-bit designs, and the advanced DEM guarantees low noise and distortion at all signal levels. ORDERING INFORMATION CS4397-KS CDB4397 SERIAL INTERFACE SOFT MUTE AND FORMAT SELECT MULTI-BIT ...
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... PIN DESCRIPTION - DSD MODE .............................................................................. 23 6.0 PIN DESCRIPTION - 8X INTERPOLATOR MODE .................................................... 24 7.0 APPLICATIONS .......................................................................................................... 25 7.1 Recommended Power-up Sequence ................................................................. 25 8.0 CONTROL PORT INTERFACE .................................................................................. 26 8.1 SPI Mode ........................................................................................................... Mode ........................................................................................................... 26 8.2 Memory Address Pointer (MAP) ....................................................................... 26 9.0 PARAMETER DEFINITIONS ...................................................................................... 33 10.0 REFERENCES .......................................................................................................... 33 11.0 PACKAGE DIMENSIONS ......................................................................................... 34 2 CS4397 DS333PP1 ...
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... Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade- marks and service marks can be found at http://www.cirrus.com. DS333PP1 2 C Mode ................................................................. .......................................................................................... 32 CS4397 3 ...
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... TBD A-Weighted TBD unweighted TBD unweighted - A-Weighted - (Note 1) THD - - - - (Note 1) unweighted TBD A-Weighted TBD unweighted TBD unweighted - A-Weighted - (Note 1) THD - - - - CS4397 Typ Max Unit 117 - dB 120 - -100 TBD dB -97 TBD dB -57 TBD 117 - dB 120 - dB 114 - -100 TBD dB -97 ...
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... PSRR - (120 Hz) - Symbol kHz Typ Max Min Typ Max 20 TBD - 20 TBD TBD TBD - TBD TBD TBD TBD - TBD TBD 0 0 Typ Max Min TBD 1.4VREF TBD - 0.5VREF - - 0 100 - - 2.0 TBD 100 - 90 - CS4397 Unit Unit Vpp VDC dB ppm/° ...
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... kHz Fs = 44.1 kHz kHz (Note 4) to -0.1 dB corner corner -0.017 .570 (Note 5) tgd (Note 4) to -0.1 dB corner corner 0.635 (Note 5) tgd CS4397 Min Typ Max - - 0.470 - - 0.492 - +0.015 - - ±0.0001 - - 102 - - - 37/ ± ...
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... Notes: 8. Assumes a DSD modulation index of 0.7. DS333PP1 ( pF) L Symbol Min (Note 1) unweighted TBD A-Weighted TBD (Note 1) THD -20 dB -60 dB (Note 8) TBD (Note 4) to -0.1 dB corner corner -0.013 tgd CS4397 = 25 °C; Logic "1" 5V; Typ Max 117 - 120 - - -100 TBD - -94 TBD - -54 TBD 1.2VREF TBD - 0.5VREF - - 0.1 - ...
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... Group Delay Notes: 9. Measurement Bandwidth is 6. Symbol (Note 1) unweighted TBD A-Weighted TBD (Note 1) THD -20 dB -60 dB TBD (Note 4) to -0.1 dB corner corner -0.0008 6.08 (Note 9) tgd CS4397 ( °C; Logic "1" Min Typ Max 117 - 120 - - -100 TBD - -97 TBD - -57 TBD 0.7VREF ...
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... VD = 3.0V - 5.25V) A Symbol (AGND = 0 V, all voltages with respect to ground.) Symbol VA VD VREF IND stg (DGND = 0V; all voltages with respect to ground) Symbol Min VD 3.0 VA 4.75 VREF TBD T -10 A CS4397 Min Typ Max Units ± Min Max Unit -0.3 6 ...
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... Fs (Single-speed 256 Fs, (Single-speed 384 Fs, (Single-speed 512 Fs, (Single-speed 768 Fs, (Single-speed mode) (Double-speed mode) (Quad-speed mode) t slrd t slrs t sdlrs t sdh t slrs t slrd t sdlrs Figure 1. Serial Audio Input Timing CS4397 Min Typ Max Unit kHz 50 - 100 kHz 100 - 200 kHz 4.096 - 12.8 MHz 6 ...
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... Logic 0 = AGND = DGND; Logic A Symbol (64x Oversampled) (128x Oversampled) (CLKMODE = 0) (CLKMODE = 1) (All DSD modes) t sclkl t sclkh (64x Oversampled) (128x Oversampled) t sdlrs t sdh t sclkl t t sdlrs sdh CS4397 Min Typ Max Unit 1.024 - 3.2 Mb/s 2.048 - 6.4 Mb/s 4.096 - 12.8 MHz 6.144 - 19.2 MHz ...
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... Symbol (Note 10) Fs (MCLK = 32×Fs) (MCLK = 48×Fs) (MCLK = 64×Fs) (MCLK = 96×Fs) t slrd t slrs t sdlrs t sdh t slrs t slrd t t sdlrs Figure 3. Serial Audio Input Timing CS4397 (T = -10 to 70°C; A Min Typ Max 128 - 400 4.096 - 12.8 6.144 - 19.2 8.192 - 25.6 12.288 - 28.4 40 ...
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... Repeated Start t high t t sud t sust hdd 2 Figure Control Port Timing CS4397 = 30 pF) L Min Max Unit - 100 KHz 500 - 4.7 - 4.0 - 4.7 - 4 250 - - 1 - 300 4.7 - Stop susp hdst ...
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... Figure 5. SPI Control Port Timing = 30 pF) L Min Max - 6 500 - 500 - 1 100 r2 - 100 all other times. spi t csh CS4397 Unit MHz ns ns µ DS333PP1 ...
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... M3 (AD1/CDIN) 2 FILT- M4 (AD0/CS) 16 C/H CMOUT CS4397 12 AOUTL- LRCK 11 SCLK AOUTL+ 13 SDATA MUTEC 15 MUTE AOUTR- 1 RST 10 MCLK AOUTR+ DGND AGND CS4397 +5V + Analog 1.0 F 0.1 µf +5V 28 Analog 0.1 µf 27 0.1 µf 100 µ 0.1 µf 5.6 µ Analog Conditioning Analog Conditioning 20 15 ...
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... The analog outputs will ramp to a normal state when this function transitions from the enabled to disabled state. The ramp requires 1152 left/right clock cycles in Single Speed, 2304 cycles in Double Speed and 4608 cycles in Quad Speed mode. The MUTEC will go high immediately on disabling of MUTE. MUTE 0 Enabled 1 Disabled Table MODE MODE CS4397 PDN PDN DS333PP1 ...
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... CAL MUTE Access and SPI. Default Powered Down Function: The analog and digital sections will be placed into a power-down mode when this function is enabled. This bit must be cleared to resume normal operation. PDN 0 Disabled 1 Enabled Table 3. DS333PP1 MODE CS4397 PDN PDN 17 ...
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... SCLK AGND 11 18 LRCK MUTEC 12 17 SDATA C MUTE 14 15 CS4397 Voltage Reference Reference Filter Reference Ground Common ModeS Voltage Differential Output Differential Output Analog Power Analog Ground Differential Output Differential Output Analog Ground Mute Control Control port/Hardware select Soft Mute DS333PP1 ...
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... DS333PP1 MCLK (MHz) 384x 512x 12.2880 16.3840 16.9344 22.5792 18.4320 24.5760 MCLK (MHz) 192x 256x 12.2880 16.3840 16.9344 22.5792 18.4320 24.5760 MCLK (MHz) 96x 128x 16.9344 22.5792 18.4320 24.5760 CS4397 768x 24.5760 33.8688 36.8640 384x 24.5760 33.8688 36.8640 192x 33.8688 36.8640 19 ...
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... Differential Analog Outpus - AOUTR- , AOUTR+ and AOUTL- , AOUTL+ Pins 19, 20, 23 and 24, Outputs Function: The full scale differential analog output level is specified in the Analog Characteristics specifications table. Analog Power - VA Pin 22, Input Function: Power for the analog and reference circuits. Typically 5VDC. 20 CS4397 DS333PP1 ...
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... C mode, AD0 is a chip address bit used to enable the control port interface in SPI mode. The device will enter the SPI mode at anytime a high to low transition is detected on this pin. Once the device has entered the SPI mode, it will remain until either the part is reset or undergoes a power-down cycle. DS333PP1 CS4397 21 ...
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... Serial Control Data I/O - SDA/CDOUT Pin 5, Input/Output Function mode, SDA is a data input/output. CDOUT is the control data output for the control port interface in SPI mode Mode Select Pin 14, Input Function: This pin is not used in Control Port Mode and must be terminated to ground. 22 CS4397 DS333PP1 ...
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... DSD_R MUTE 14 15 CLKMODE CS4397 Refer to PCM mode Refer to PCM mode Refer to PCM mode Refer to PCM mode Refer to PCM mode Refer to PCM mode Refer to PCM mode Refer to PCM mode Refer to PCM mode Refer to PCM mode Refer to PCM mode Refer to PCM mode ...
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... DIR 14 15 MCLK (MHz) 48x 64x 12.2880 16.384 16.9344 22.579 18.4320 24.576 CS4397 VREF Refer to PCM mode FILT+ Refer to PCM mode FILT- Refer to PCM mode CMOUT Refer to PCM mode AOUTL- Refer to PCM mode AOUTL+ Refer to PCM mode VA Refer to PCM mode ...
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... APPLICATIONS 7.1 Recommended Power-up Sequence 1. Hold RST low until the power supplies, master, and left/right clocks are stable. 2. Bring RST high. DS333PP1 CS4397 25 ...
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... The control port has 2 modes: SPI and operation is desired, AD0/CS should be tied DGND. If the CS4397 ever detects a high to low transition on AD0/CS after power-up, SPI mode will be selected. 8.1 SPI Mode In SPI mode the CS4397 chip select signal, CCLK is the control port bit clock, CDIN is the input data line from the microcontroller, CDOUT is the data output and the chip address is 0010000 ...
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... Note: If operation is a write, this byte contains the Memory Address Pointer, MAP. DS333PP1 CHIP MAP ADDRESS 0010000 MSB R/W byte 1 MAP = Memory Address Pointer = 0 Figure 7. Control Port Timing, SPI mode ADDR DATA R/W ACK AD0 1-8 Figure 8. Control Port Timing, I CS4397 DATA LSB byte n Note 1 DATA ACK ACK 1-8 Stop 2 C Mode 27 ...
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... 24-bit data, Format Right Justified 16-bit data, Format Right Justified 24-bit data, Format Right Justified 20-bit data 0 0 (DIR) Right Justified 24-bit data 0 1 (DIR 64x Oversampled DSD 0 0 128x Oversampled DSD 0 1 CS4397 FORMAT FIGURE FIGURE DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DS333PP1 ...
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... Frequency (normalized to Fs) 0.05 0.1 0.15 0.2 0.25 0.3 0.35 Frequency (normalized to Fs) 0.45 0.5 0.55 Frequency (normalized to Fs) 0.05 0.1 0.15 0.2 0.25 0.3 0.35 Frequency (normalized to Fs) CS4397 0.9 0.95 1 0.4 0.45 0.6 0.4 0.45 29 ...
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... Frequency (normalized to Fs) .05 .1 1.5 .2 0.1 0.2 0.3 0.4 Frequency (normalized to Fs) CS4397 0.66 0.68 0.7 0.35 0 5.6 6.0 6.4 1.4 1.5 1.6 .25 .3 0.5 0.6 DS333PP1 ...
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... Frequency (normalized to Fs) Figure 27. DSD Transition Band DS333PP1 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 2.5 Gain dB 0dB -10dB 2.5 3 3.5 4 CS4397 3 3.5 4 4.5 5 Frequency (normalized to Fs) Figure 26. DSD Transition Band T1=50 µ µ Frequency 3.183 kHz 10.61 kHz Figure 28. De-Emphasis Curve 5 ...
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... Figure 32. Format 3, Right Justified, 24-Bit Data WCKI BCKI DIL/DIR LSB MSB LSB MSB - Figure 29. Format 0, Left Justified + LSB MSB - Figure 30. Format Figure 31. Format 2, Right Justified, 16-Bit Data Figure 33. Format 4, 8x Interpolator Mode CS4397 Right Channel + LSB Right Channel + LSB 2 S Right Channel Right Channel ...
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... Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992. 2) CDB4397 Evaluation Board Datasheet 2 3) “The I C-Bus Specification: Version 2.0” Philips Semiconductors, December 1998. http://www.semiconductors.philips.com DS333PP1 CS4397 33 ...
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... MAX 0.093 0.104 0.004 0.012 0.013 0.020 0.009 0.013 0.697 0.713 0.29G10 0.299 1 0.040 0.060 0.394 0.419 0.016 0.050 0° 8° JEDEC #: MS-013 CS4397 MILLIMETERS MIN MAX 2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 17.70 18.10 7.40 7.60 1.02 1.52 10 ...
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Notes • ...
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