DS92CK16TMTC National Semiconductor, DS92CK16TMTC Datasheet
DS92CK16TMTC
Manufacturer Part Number
DS92CK16TMTC
Description
IC,Six Distributed-Output Clock Driver,CMOS,TSSOP,24PIN,PLASTIC
Manufacturer
National Semiconductor
Datasheets
1.DS92CK16TMTC.pdf
(12 pages)
2.DS92CK16TMTC.pdf
(11 pages)
3.DS92CK16TMTC.pdf
(11 pages)
Specifications of DS92CK16TMTC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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© 2006 National Semiconductor Corporation
DS92CK16
3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver
General Description
The DS92CK16 1 to 6 Clock Buffer/Bus Transceiver is a one
to six CMOS differential clock distribution device utilizing Bus
Low Voltage Differential Signaling (BLVDS) technology. This
clock distribution device is designed for applications requir-
ing ultra low power dissipation, low noise, and high data
rates. The BLVDS side is a transceiver with a separate
channel acting as a return/source clock.
The DS92CK16 accepts LVDS (300 mV typical) differential
input levels, and translates them to 3V CMOS output levels.
An output enable pin OE , when high, forces all CLK
high.
The device can be used as a source synchronous driver. The
selection of the source driving is controlled by the CrdCLK
and DE pins. This device can be the master clock, driving the
inputs of other clock I/O pins in a multipoint environment.
Easy master/slave clock selection is achieved along a back-
plane.
Function Diagram and Truth Table
L = Low Logic State
H = High Logic State
X = Irrelevant
Z = TRI-STATE
TRI-STATE
OE DE
H
L
L
H
H
H
®
is a registered trademark of National Semiconductor Corporation.
CrdCLK
Receive Mode Truth Table
X
X
X
INPUT
IN
(CLKI/O+)–(CLKI/O−)
VID≤ −0.07V
VID≥ 0.07V
X
DS101082
OUTPUT
CLK
OUT
H
H
L
OUT
pins
IN
Features
n Master/Slave clock selection in a backplane application
n 125 MHz operation (typical)
n 100 ps duty cycle distortion (typical)
n 50 ps channel to channel skew (typical)
n 3.3V power supply design
n Glitch-free power on at CLKI/O pins
n Low Power design (20 mA
n Accepts small swing (300 mV typical) differential signal
n Industrial temperature operating range (-40˚C to +85˚C)
n Available in 24-pin TSSOP Packaging
OE
H
H
H
levels
L
L
DE CrdCLK
H
L
L
L
L
INPUT
Driver Mode Truth Table
H
H
X
L
L
IN
CLK/I/O+
H
H
Z
L
L
@
3.3V static)
10108201
OUTPUT
CLKI/O−
H
H
L
L
Z
www.national.com
April 2006
CLK
H
H
H
H
L
OUT
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