DSPIC30F1010-20E/SO Microchip Technology, DSPIC30F1010-20E/SO Datasheet - Page 8

• Manufacturer Part Number: DSPIC30F1010-20E/SO
• Description: 6KB, Flash, 256bytes-RAM, 30MIPS, 21I/O, 16-bit Family,nanoWatt 28 SOIC .300in T
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F1010-20E/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 6KB (2K x 24)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300023 - KIT DEMO DSPICDEM SMPS BUCKDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

5.7
5.7.1
The dsPIC30F SMPS has Configuration bits stored
in seven 16-bit registers. These bits can be set or
cleared to select various device configurations.
There are two types of Configuration bits: system
operation bits and code-protect bits. The system
operation bits determine the power-on settings for
system level components such as the oscillator and
Watchdog Timer. The code-protect bits prevent
program memory from being read and written.
TABLE 5-3:
DS70284C-page 8
FBS
Reserved
FGS
FOSCSEL F80006
FOSC
FWDT
FPOR
FICD
Legend: — = unimplemented bit, read as ‘0’
Note 1:
Name
Configuration Bits Programming
Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
OVERVIEW
F80000
F80002
F80004
F80008
F8000A
F8000C
F8000E
Address
dsPIC30F SMPS FAMILY DEVICE CONFIGURATION REGISTER MAP
FWDTEN WINDIS
BKBUG
Bit 7
FCKSM<1:0>
—
—
—
—
—
Bit 6
—
—
—
—
—
—
FRANGE
Bit 5
—
—
—
—
—
—
—
WDTPRE
Bit 4
—
—
—
—
—
—
—
Table 5-3
SMPS devices, and
bits.
Note:
shows the Configuration registers for the
Bit 3
If user software performs an erase opera-
tion on the configuration fuse, it must be
followed by a write operation to this fuse
with the desired value, even if the desired
value is the same as the state of the
erased fuse.
—
—
—
—
—
—
BSS<2:0>
Table 5-4
OSCIOFNC
WDTPOST<3:0>
© 2010 Microchip Technology Inc.
Bit 2
—
—
—
GSS<1:0>
FPWRT<2:0>
describes the individual
Bit 1
POSCMD<1:0>
FNOSC<1:0>
—
ICS<1:0>
GWRP
BWRP
Bit 0
—