DSPIC30F6012AT-20E/PF Microchip Technology, DSPIC30F6012AT-20E/PF Datasheet - Page 25

• Manufacturer Part Number: DSPIC30F6012AT-20E/PF
• Description: 16-bit MCU/DSP 30MIPS 144KB 64 TQFP 14x14x1mm T/R
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6012AT-20E/PF

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 144KB (48K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT4 - SOCKET TRAN ICE 64MQFP/TQFPAC164313 - MODULE SKT FOR PM3 64PFAC30F002 - MODULE SOCKET DSPIC30F 64TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

3.0
3.1
The program address space is 4M instruction words. It
is addressable by a 24-bit value from either the 23-bit
PC, table instruction Effective Address (EA), or data
space EA, when program space is mapped into data
space as defined by
space address is incremented by two between succes-
sive program words in order to provide compatibility
with data space addressing.
© 2011 Microchip Technology Inc.
Note:
MEMORY ORGANIZATION
Program Address Space
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC
Programmer’s
(DS70157).
Table
dsPIC30F6011A/6012A/6013A/6014A
3-1. Note that the program
Reference
Manual”
User program space access is restricted to the lower
4M instruction word address range (0x000000 to
0x7FFFFE) for all accesses other than TBLRD/TBLWT,
which use TBLPAG<7> to determine user or configura-
tion space access. In
Address Construction, bit 23 allows access to the
Device ID, the Unit ID and the configuration bits.
Otherwise, bit 23 is always clear.
Note:
The address map shown in
Figure 3-2
memory configuration may vary across
individual devices depending on available
memory.
is conceptual, and the actual
Table
3-1, Program Space
DS70143E-page 25
Figure 3-1
and