EP9307-IR Cirrus Logic Inc, EP9307-IR Datasheet - Page 172

• Manufacturer Part Number: EP9307-IR
• Description: IC Universal Platform ARM9 SOC Prcessor
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-IR

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 272-TFBGA
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: 598-1133 - KIT DEVELOPMENT EP9307 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1255

6
VICxFIQStatus
VICxRawIntr
6-10
Vectored Interrupt Controller
EP93xx User’s Guide
31
15
31
15
Definition:
Bit Descriptions:
Address:
Definition:
Bit Descriptions:
Address:
30
14
30
14
29
13
29
13
28
12
28
12
IRQ Status Register. The VICxIRQStatus register provides the status of
interrupts after IRQ masking.
Interrupts 0 - 31 are in VIC1IRQStatus.
Interrupts 32 - 63 are in VIC2IRQStatus.
IRQStatus:
VIC1FIQStatus: 0x800B_0004 - Read Only
VIC2FIQStatus: 0x800C_0004 - Read Only
FIQ Status Register. The VICxFIQStatus register provides the status of the
interrupts after FIQ masking.
FIQStatus:
VIC1RawIntr: 0x800B_0008 - Read Only
VIC2RawIntr: 0x800C_0008 - Read Only
27
27
11
11
26
10
26
10
Copyright 2007 Cirrus Logic
25
25
9
9
Shows the status of the interrupts after masking by the
VICxIntEnable and VICxIntSelect registers. A “1” indicates
that the interrupt is active, and generates an interrupt to
the ARM Core.
Shows the status of the interrupts after masking by the
VICxIntEnable and VICxIntSelect registers. A “1” indicates
that the interrupt is active, and generates an interrupt to
the ARM Core.
24
24
8
8
FIQStatus
FIQStatus
RawIntr
RawIntr
23
23
7
7
22
22
6
6
21
21
5
5
20
20
4
4
19
19
3
3
18
18
2
2
17
17
1
1
DS785UM1
16
16
0
0