EP9307-IR Cirrus Logic Inc, EP9307-IR Datasheet - Page 672

IC Universal Platform ARM9 SOC Prcessor

EP9307-IR

Manufacturer Part Number
EP9307-IR
Description
IC Universal Platform ARM9 SOC Prcessor
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets

Specifications of EP9307-IR

Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
14
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
272-TFBGA
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9307A-Z
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
598-1133 - KIT DEVELOPMENT EP9307 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Other names
598-1255

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9307-IR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Part Number:
EP9307-IRZ
Manufacturer:
CIRRUS
Quantity:
3 468
Part Number:
EP9307-IRZ
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Part Number:
EP9307-IRZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
21
I2STXLinCtrlData
I2STXCtrl
21-16
I
EP93xx User’s Guide
2
S Controller
31
15
31
15
Address:
Default:
Definition:
Bit Descriptions:
Address:
Default:
30
14
30
14
29
13
29
13
28
12
28
12
0x8082_0028 - Read/Write
0x0000_0000
Line Control Data Register
RSVD:
Left_Right_Justify: Determines how the data word is justified when being
TXUF_REPEAT_SAMPLE:On TX underflow, the I
TXDIR:
0x8082_002C - Read/Write
0x0000_0000
27
11
27
11
26
10
RSVD
26
10
25
9
25
9
Copyright 2007 Cirrus Logic
24
8
RSVD
Reserved. Unknown During Read.
transmitted on the sdo line output.
0 - left justified.
1 - right justified
zeros if this bit is “1”.
If this bit is “0” the I
underflow.
Transmit data shift direction.
0 - MSB first
1 - LSB first
23
24
7
8
22
6
RSVD
RSVD
23
7
21
5
22
6
20
4
2
21
5
S controller repeats the last sample on
19
3
20
4
Left_Right_Justify
18
2
2
19
3
S controller transmits all
18
2
TXUF_REPEAT_SAMPLE
TXUFIE
17
1
17
1
TXEMPTY_int_level
DS785UM1
16
0
TXDIR
16
0

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