KS8721BL Micrel Inc, KS8721BL Datasheet - Page 13

• Manufacturer Part Number: KS8721BL
• Description: Special Function IC
• Manufacturer: Micrel Inc
• Type: Transceiverr

Specifications of KS8721BL

• Leaded Process Compatible: No
• Peak Reflow Compatible (260 C): No
• Number Of Drivers/receivers: 1/1
• Protocol: MII, RMII
• Voltage - Supply: 2.375 V ~ 2.625 V
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: 576-1007 - BOARD EVAL EXPERIMENT KS8721BL
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant

asserted. For 10BASE-T links, CRS assertion is based on reception of valid preamble, and de-assertion on reception of an
end-of-frame (EOF) marker.
Collision: Whenever the line state is half-duplex and the transmitter and receiver are active at the same time, the KS8721BL/
SL asserts its collision signal, which is asynchronous to any clock.
RMII (Reduced MII) Data Interface
RMII interface specifies a low-pin count, Reduced Media Independent Interface (RMII) intended for use between Ethernet
PHYs and Switch or Repeater ASICs. It is fully compliant with IEEE 802.3u [2].
This interface has the following characteristics:
RMII Signal Definition
Reference Clock (REF_CLK)
REF_CLK is a continuous 50MHz clock that provides the timing reference for CRS_DV, RXD[1:0], TX_EN, TXD[1:0], and
RX_E. REF_CLK is sourced by the MAC or an external source. Switch implementations may choose to provide REF_CLK as
an input or an output depending on whether they provide a REF_CLK output or rely on an external clock distribution device.
Each PHY device must have an input corresponding to this clock but may use a single clock input for multiple PHYs
implemented on a single IC.
Carrier Sense/Receive Data Valid (CRS_DV)
CRS_DV is asserted asynchronously on detection of carrier due to the criteria relevant to the operating mode. That is, in
10BASE-T mode, when squelch is passed or in 100BASE-X mode when 2 noncontiguous zeroes in 10 bits are detected, the
carrier is detected.
Loss-of-carrier results in the de-assertion of CRS_DV synchronous to REF_CLK. As carrier criteria are met, CRS_DV remains
continuously asserted from the first recovered di-bit of the frame through the final recovered di-bit and is negated prior to the
first REF_CLK that follows the final di-bit.
The data on RXD[1:0] is considered valid once CRS_DV is asserted. However, since the assertion of CRS_DV is asynchronous
relative to REF_CLK, the data on RXD[1:0] remains as “00” until proper receive signal decoding takes place (see “Definition
of RXD[1:0] Behavior”).
Receive Data [1:0] (RXD[1:0])
RXD[1:0] transitions synchronously to REF_CLK. For each clock period in which CRS_DV is asserted, RXD[1:0] transfers two
bits of recovered data from the PHY. In some cases (e.g., before data recovery or during error conditions), a predetermined
value for RXD[1:0] is transferred instead of recovered data. RXD[1:0] remains as “00” to indicate idle when CRS_DV is de-
asserted. Values of RXD[1:0] other than “00” when CRS_DV is de-asserted are reserved for out-of-band signalling (to be
defined). Values other than “00” on RXD[1:0] while CRS_DV is de-asserted are ignored by the MAC/repeater. Upon assertion
of CRS_DV, the PHY ensures that RXD[1:0]=00 until proper receive decoding takes place.
Transmit Enable (TX_EN)
Transmit Enable TX_EN indicates that the MAC is presenting di-bits on TXD[1:0] on the RMII for transmission. TX_EN is
asserted synchronously with the first nibble of the preamble and remains asserted while all transmitted di-bits are presented
May 2004
KS8721BL/SL
Signal Name
REF_CLK
CRS_DV
RXD[1:0]
TX_EN
TXD[1:0]
RX_ER
• It is capable of supporting 10Mbps and 100Mbps data rates.
• A single clock reference is sourced from the MAC to PHY (or from an external source).
• It provides independent 2-bit wide (di-bit) transmit and receive data paths.
• It uses TTL signal levels compatible with common digital CMOS ASIC processes.
Direction
(w/respect to the PHY)
Input
Output
Output
Input
Input
Output
Direction
(w/respect to the MAC)
Input or Output
Input
Input
Output
Output
Input (Not Required)
13
Use
Synchronous clock reference for receive, transmit and
control interface
Carrier Sense/Receive Data Valid
Receive Data
Transmit Enable
Transmit Data
Receive Error
M9999-051704
Micrel