PIC16F648A-E/SO Microchip Technology, PIC16F648A-E/SO Datasheet - Page 89
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,18PIN,PLASTIC](/photos/6/76/67656/150-18-soic_sml.jpg)
PIC16F648A-E/SO
Manufacturer Part Number
PIC16F648A-E/SO
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,18PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F627A-IP.pdf
(180 pages)
3.PIC16F627A-IP.pdf
(8 pages)
4.PIC16F627A-IP.pdf
(22 pages)
Specifications of PIC16F648A-E/SO
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
18-SOIC (7.5mm Width)
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SCI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
16
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
I3DBF648 - BOARD DAUGHTER ICEPIC3
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F648A-E/SO
Manufacturer:
INTEL
Quantity:
5
FIGURE 12-10:
12.5
Synchronous Slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the RB2/TX/CK pin (instead of being supplied internally
in Master mode). This allows the device to transfer or
receive data while in Sleep mode. Slave mode is
entered by clearing bit CSRC (TXSTA<7>).
12.5.1
The operation of the Synchronous Master and Slave
modes are identical except in the case of the Sleep
mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
a)
b)
c)
d)
e)
© 2009 Microchip Technology Inc.
SREN bit
CREN bit
RCIF bit
(Interrupt)
Read
RXREG
RB2/TX/CK pin
WRITE to
Bit SREN
RB1/RX/DT pin
The first word will immediately transfer to the
TSR register and transmit.
The second word will remain in TXREG register.
Flag bit TXIF will not be set.
When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will now be
set.
If enable bit TXIE is set, the interrupt will wake
the chip from Sleep and if the global interrupt is
enabled, the program will branch to the interrupt
vector (0004h).
USART Synchronous Slave Mode
Note:
Q2
USART SYNCHRONOUS SLAVE
TRANSMIT
Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4
‘0’
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRG = 0.
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
bit 0
Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3 Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4
bit 1
bit 2
PIC16F627A/628A/648A
bit 3
Follow these steps when setting up a Synchronous
Slave Transmission:
1.
2.
3.
4.
5.
6.
7.
8.
bit 4
TRISB<1> and TRISB<2> should both be set to
‘1’ to configure the RB1/RX/DT and RB2/TX/CK
pins as inputs. Output drive, when required, is
controlled by the peripheral circuitry.
Enable the synchronous slave serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
Clear bits CREN and SREN.
If interrupts are desired, then set enable bit
TXIE.
If 9-bit transmission is desired, then set bit TX9.
Enable the transmission by setting enable bit
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the TXREG
register.
bit 5
bit 6
bit 7
DS40044G-page 89
Q1Q2Q3Q4
‘0’