PIC16F767-E/ML Microchip Technology, PIC16F767-E/ML Datasheet - Page 175

• Manufacturer Part Number: PIC16F767-E/ML
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F767-E/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.6
1997 Microchip Technology Inc.
T0CKI pin
CLKOUT (=Fosc/4)
WDT Enable bit
Watchdog
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
Timer
TMR0 Prescaler
T0SE
An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the
Watchdog Timer
the Timer0 description. Thus, a prescaler assignment for the Timer0 module means that there is
no postscaler for the Watchdog Timer, and vice-versa.
The PSA and PS2:PS0 bits (OPTION<3:0>) determine the prescaler assignment and prescale
ratio.
When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g.,
CLRF TMR0, MOVWF TMR0, BSF TMR0,x....etc.) will clear the prescaler. When assigned to WDT,
a CLRWDT instruction will clear the prescaler along with the Watchdog Timer. The prescaler is not
readable or writable.
Figure 11-6: Block Diagram of the Timer0/WDT Prescaler
Note:
0
1
PSA
M
U
X
There is only one prescaler available which is mutually exclusively shared between
the Timer0 module and the Watchdog Timer.
0
1
T0CS
(Figure
M
U
X
0
8-bit Prescaler
8 - to - 1MUX
11-6). For simplicity, this counter is being referred to as “prescaler” in
Time-out
8
M U X
WDT
1
0
1
PSA
M
U
X
PSA
Section 11. Timer0
PS2:PS0
Cycles
SYNC
2
TMR0 reg
Data Bus
8
DS31011A-page 11-7
Set T0IF flag bit
on Overflow
11