PIC16F873-04E/SO Microchip Technology, PIC16F873-04E/SO Datasheet - Page 381
PIC16F873-04E/SO
Manufacturer Part Number
PIC16F873-04E/SO
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,28PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F873-04SO.pdf
(218 pages)
4.PIC16F873-04SO.pdf
(5 pages)
5.PIC16F873-04SO.pdf
(5 pages)
6.PIC16F873-04SO.pdf
(4 pages)
Specifications of PIC16F873-04E/SO
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC16F87304E/SO
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F873-04SO PDF datasheet #3
- PIC16F873-04SO PDF datasheet #4
- PIC16F873-04SO PDF datasheet #5
- PIC16F873-04SO PDF datasheet #6
- Current page: 381 of 688
- Download datasheet (3Mb)
20.12
1997 Microchip Technology Inc.
Initialization
The code in
of the PIC16C62X devices. RA3 and RA4 are configured as digital output. RA0 and RA1 are con-
figured as the V- inputs and RA2 as the V+ input to both comparators.
Example 20-1:
FLAG_REG
;
CLRF
CLRF
ANDLW
IORWF
MOVLW
MOVWF
BSF
MOVLW
MOVWF
BCF
CALL
MOVF
BCF
BSF
BSF
BCF
BSF
BSF
Example 20-1
EQU
FLAG_REG
PORTA
0xC0
FLAG_REG,F
0x03
CMCON
STATUS,RP0
0x07
TRISA
STATUS,RP0
DELAY 10
CMCON,F
PIR1,CMIF
STATUS,RP0
PIE1,CMIE
STATUS,RP0
INTCON,PEIE
INTCON,GIE
Initializing Comparator Module (PIC16C62X)
0X20
depicts example steps required to configure the comparator module
; Init flag register
; Init PORTA
; Mask comparator bits
; Store bits in flag register
; Init comparator mode
; CM<2:0> = 011
; Select Bank1
; Initialize data direction
; Set RA<2:0> as inputs, RA<4:3> as outputs,
;
; Select Bank0
; 10 s delay
; Read
; Clear pending interrupts
; Select Bank1
; Enable comparator interrupts
; Select Bank0
; Enable peripheral interrupts
; Global interrupt enable
Section 20. Comparator
TRISA<7:5> always read ‘0’
CMCON to end change condition
DS31020A-page 20-11
20
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