PIC16F874A-E/L Microchip Technology, PIC16F874A-E/L Datasheet - Page 324
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,44PIN,PLASTIC](/photos/6/63/66325/150-44-plcc_sml.jpg)
PIC16F874A-E/L
Manufacturer Part Number
PIC16F874A-E/L
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,44PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16C770-ISO.pdf
(8 pages)
4.PIC16F873A-ISO.pdf
(234 pages)
5.PIC16F873A-ISO.pdf
(6 pages)
6.PIC16F873A-ISO.pdf
(4 pages)
7.PIC16F873A-ISO.pdf
(6 pages)
8.PIC16F873A-ISO.pdf
(4 pages)
9.PIC16F873A-ISO.pdf
(22 pages)
Specifications of PIC16F874A-E/L
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DVA16XL441 - ADAPTER DEVICE ICE 44PLCC309-1040 - ADAPTER 44-PLCC ZIF TO 40-DIP309-1039 - ADAPTER 44-PLCC TO 40-DIP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F874A-E/L
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16C770-ISO PDF datasheet #3
- PIC16F873A-ISO PDF datasheet #4
- PIC16F873A-ISO PDF datasheet #5
- PIC16F873A-ISO PDF datasheet #6
- PIC16F873A-ISO PDF datasheet #7
- PIC16F873A-ISO PDF datasheet #8
- PIC16F873A-ISO PDF datasheet #9
- Current page: 324 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
17.4.15
17.4.16
17.4.17
DS31017A-page 17-48
BRG overflow,
Release SCL,
If SCL = 1 Load BRG with
SSPADD<6:0>, and start count
to measure high time interval
SCL
SDA
Clock Arbitration
Sleep Operation
Effect of a Reset
Clock arbitration occurs when the master, during any receive, transmit, or Repeated Start/stop
condition de-asserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float
high, the baud rate generator (BRG) is suspended from counting until the SCL pin is actually
sampled high. When the SCL pin is sampled high, the baud rate generator is reloaded with the
contents of SSPADD<6:0> and begins counting. This ensures that the SCL high time will always
be at least one BRG rollover count in the event that the clock is held low by an external device
(Figure
Figure 17-33: Clock Arbitration Timing in Master Transmit Mode
While in sleep mode, the I
or complete byte transfer occurs wake the processor from sleep (if the MSSP interrupt is
enabled).
A reset disables the MSSP module and terminates the current transfer.
T
17-33).
BRG
BRG overflow occurs,
Release SCL, Slave device holds SCL low.
T
BRG
2
C module can receive addresses or data, and when an address match
Preliminary
SCL line sampled once every machine cycle (T
Hold off BRG until SCL is sampled high.
T
SCL = 1 BRG starts counting
clock high interval.
BRG
1997 Microchip Technology Inc.
osc
4).
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