PIC16F884-E/ML Microchip Technology, PIC16F884-E/ML Datasheet - Page 210

• Manufacturer Part Number: PIC16F884-E/ML
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,44PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F884-E/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F882/883/884/886/887
13.4.17
An SSP Mask (SSPMSK) register is available in I
Slave mode as a mask for the value held in the
SSPSR register during an address comparison
operation. A zero (‘0’) bit in the SSPMSK register has
the effect of making the corresponding bit in the
SSPSR register a “don’t care”.
This register is reset to all ‘1’s upon any Reset
condition and, therefore, has no effect on standard
SSP operation until written with a mask value.
REGISTER 13-4:
DS41291F-page 208
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-1
bit 0
Note 1: When SSPCON bits SSPM<3:0> = 1001, any reads or writes to the SSPADD SFR address are accessed
R/W-1
MSK7
2: In all other SSP modes, this bit has no effect.
SSP MASK REGISTER
through the SSPMSK register.
MSK<7:1>: Mask bits
1 = The received address bit n is compared to SSPADD<n> to detect I
0 = The received address bit n is not used to detect I
MSK<0>: Mask bit for I
I
1 = The received address bit 0 is compared to SSPADD<0> to detect I
0 = The received address bit 0 is not used to detect I
2
C Slave mode, 10-bit Address (SSPM<3:0> = 0111):
R/W-1
MSK6
SSPMSK: SSP MASK REGISTER
W = Writable bit
‘1’ = Bit is set
R/W-1
MSK5
2
C Slave mode, 10-bit Address
R/W-1
MSK4
2
C
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(1)
R/W-1
MSK3
This register must be initiated prior to setting
SSPM<3:0> bits to select the I
10-bit address).
This register can only be accessed when the appropriate
mode is selected by bits (SSPM<3:0> of SSPCON).
The SSP Mask register is active during:
• 7-bit Address mode: address compare of A<7:1>.
• 10-bit Address mode: address compare of A<7:0>
only. The SSP mask has no effect during the
reception of the first (high) byte of the address.
2
2
C address match
(2)
C address match
R/W-1
MSK2
© 2009 Microchip Technology Inc.
2
2
C address match
C address match
x = Bit is unknown
R/W-1
MSK1
2
C Slave mode (7-bit or
MSK0
R/W-1
(2)
bit 0