PIC16F884-E/ML Microchip Technology, PIC16F884-E/ML Datasheet - Page 35

• Manufacturer Part Number: PIC16F884-E/ML
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,44PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F884-E/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.2.2.5
The PIE2 register contains the interrupt enable bits, as
shown in Register 2-5.
REGISTER 2-5:
© 2009 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OSFIE
R/W-0
PIE2 Register
OSFIE: Oscillator Fail Interrupt Enable bit
1 = Enables oscillator fail interrupt
0 = Disables oscillator fail interrupt
C2IE: Comparator C2 Interrupt Enable bit
1 = Enables Comparator C2 interrupt
0 = Disables Comparator C2 interrupt
C1IE: Comparator C1 Interrupt Enable bit
1 = Enables Comparator C1 interrupt
0 = Disables Comparator C1 interrupt
EEIE: EEPROM Write Operation Interrupt Enable bit
1 = Enables EEPROM write operation interrupt
0 = Disables EEPROM write operation interrupt
BCLIE: Bus Collision Interrupt Enable bit
1 = Enables Bus Collision interrupt
0 = Disables Bus Collision interrupt
ULPWUIE: Ultra Low-Power Wake-up Interrupt Enable bit
1 = Enables Ultra Low-Power Wake-up interrupt
0 = Disables Ultra Low-Power Wake-up interrupt
Unimplemented: Read as ‘0’
CCP2IE: CCP2 Interrupt Enable bit
1 = Enables CCP2 interrupt
0 = Disables CCP2 interrupt
R/W-0
C2IE
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
W = Writable bit
‘1’ = Bit is set
R/W-0
C1IE
PIC16F882/883/884/886/887
R/W-0
EEIE
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
BCLIE
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
ULPWUIE
R/W-0
x = Bit is unknown
U-0
—
DS41291F-page 33
CCP2IE
R/W-0
bit 0