PIC16F916T-I/SS Microchip Technology, PIC16F916T-I/SS Datasheet - Page 166

• Manufacturer Part Number: PIC16F916T-I/SS
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SSOP,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F916T-I/SS

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 352 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA160011 - DAUGHTER BOARD PICDEM LCD 16F91X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F913/914/916/917/946
10.9
The LCD timing generation provides an interrupt that
defines the LCD frame timing.
A new frame is defined to begin at the leading edge of
the COM0 common signal. The interrupt will be set
immediately after the LCD controller completes access-
ing all pixel data required for a frame. This will occur at
a fixed interval before the frame boundary (T
shown in Figure 10-17. The LCD controller will begin to
access data for the next frame within the interval from
the interrupt to when the controller begins to access
data after the interrupt (T
ten within T
begin to access the data for the next frame.
When the LCD driver is running with Type-B waveforms
and the LMUX<1:0> bits are not equal to ‘00’ (static
drive), there are some additional issues that must be
addressed. Since the DC voltage on the pixel takes two
frames to maintain zero volts, the pixel data must not
change between subsequent frames. If the pixel data
were allowed to change, the waveform for the odd
frames would not necessarily be the complement of the
waveform generated in the even frames and a DC
FIGURE 10-17:
DS41250F-page 164
COM0
COM1
COM2
COM3
T
T
FWR
FINT
LCD Interrupts
FWR
= T
= (T
(T
, as this is when the LCD controller will
FRAME
FWR
FWR
/2 – (2 T
/2 – (1 T
Frame
Boundary
/2*(LMUX<1:0> + 1) + T
(EXAMPLE – TYPE-B, NON-STATIC)
WAVEFORMS AND INTERRUPT TIMING IN QUARTER-DUTY CYCLE DRIVE
FWR
CY
CY
). New data must be writ-
+ 40 ns)) → minimum = 1.5(T
+ 40 ns)) → maximum = 1.5(T
CY
/2
FINT
), as
2 Frames
FRAME
FRAME
Frame
Boundary
/4) – (2 T
/4) – (1 T
component would be introduced into the panel.
Therefore, when using Type-B waveforms, the user
must synchronize the LCD pixel updates to occur within
a subframe after the frame interrupt.
To correctly sequence writing while in Type-B, the
interrupt will only occur on complete phase intervals. If
the user attempts to write when the write is disabled,
the WERR bit of the LCDCON register is set and the
write does not occur.
Note:
CY
CY
LCD
Interrupt
Occurs
+ 40 ns)
+ 40 ns)
The interrupt is not generated when the
Type-A waveform is selected and when the
Type-B with no multiplex (static) is
selected.
T
FWR
T
FINT
© 2007 Microchip Technology Inc.
Controller Accesses
Next Frame Data
Frame
Boundary
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0