PIC18C442-I/L Microchip Technology, PIC18C442-I/L Datasheet - Page 212

• Manufacturer Part Number: PIC18C442-I/L
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,44PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C442-I/L

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: MSSP, SPI, I2C, PSP, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: ICE2000, DM163022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3DB18C452 - BOARD DAUGHTER ICEPIC3AC164309 - MODULE SKT FOR PM3 44PLCC444-1001 - DEMO BOARD FOR PICMICRO MCUDVA16XL441 - ADAPTER DEVICE ICE 44PLCCDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18CXX2
IORLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39026C-page 210
Q Cycle Activity:
Before Instruction
After Instruction
Decode
WREG
WREG
Q1
=
=
Inclusive OR literal with WREG
[ label ]
0
(WREG) .OR. k
N,Z
The contents of WREG are OR’ed
with the eight-bit literal 'k'. The
result is placed in WREG.
1
1
literal ’k’
IORLW
Read
0000
Q2
0x9A
0xBF
k
255
IORLW k
1001
0x35
Process
Data
Q3
WREG
kkkk
Write to
WREG
Q4
kkkk
IORWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
RESULT =
WREG
RESULT =
WREG
Q1
=
=
register ’f’
Inclusive OR WREG with f
[ label ]
0
d
a
(WREG) .OR. (f)
N,Z
Inclusive OR WREG with register
'f'. If 'd' is 0, the result is placed in
WREG. If 'd' is 1, the result is
placed back in register 'f' (default).
If ’a’ is 0, the Access Bank will be
selected, overriding the BSR value.
If ’a’ = 1, then the bank will be
selected as per the BSR value
(default).
1
1
IORWF
Read
0001
Q2
0x13
0x91
0x13
0x93
f
[0,1]
[0,1]
2001 Microchip Technology Inc.
255
RESULT, 0, 1
IORWF
00da
Process
Data
Q3
ffff
dest
f [,d [,a]
destination
Write to
Q4
ffff