PIC18C442-I/L Microchip Technology, PIC18C442-I/L Datasheet - Page 59

• Manufacturer Part Number: PIC18C442-I/L
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,44PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C442-I/L

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: MSSP, SPI, I2C, PSP, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: ICE2000, DM163022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3DB18C452 - BOARD DAUGHTER ICEPIC3AC164309 - MODULE SKT FOR PM3 44PLCC444-1001 - DEMO BOARD FOR PICMICRO MCUDVA16XL441 - ADAPTER DEVICE ICE 44PLCCDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

5.1.2
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch is used to hold
8-bit data during data transfers between program
memory and data memory.
TABLE 5-1:
5.2
5.2.1
The TBLRD instructions are used to read data from
program memory to data memory.
TBLPTR points to a byte address in program space.
Executing TBLRD places the byte pointed to into TAB-
LAT. In addition, TBLPTR can be modified automati-
cally for the next Table Read operation.
Table Reads from program memory are performed one
byte at a time. The instruction will load TABLAT with the
one byte from program memory pointed to by TBLPTR.
5.2.2
The internal program memory of PIC18CXXX devices
is written in blocks. For PIC18CXX2 devices, the write
block size is 2 bytes. Consequently, Table Write opera-
tions to internal program memory are performed in
pairs, one byte at a time.
2001 Microchip Technology Inc.
Example
TBLRD*+
TBLWT*+
TBLRD*-
TBLWT*-
TBLRD+*
TBLWT+*
TBLRD*
TBLWT*
Internal Program Memory Read/
Writes
TABLAT - TABLE LATCH REGISTER
TABLE READ OVERVIEW ( TBLRD )
INTERNAL PROGRAM MEMORY
WRITE BLOCK SIZE
TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
TBLPTR is incremented before the read/write
TBLPTR is decremented after the read/write
TBLPTR is incremented after the read/write
Operation on Table Pointer
TBLPTR is not modified
5.1.3
The Table Pointer (TBLPTR) addresses a byte within
the program memory. The TBLPTR is comprised of
three SFR registers (Table Pointer Upper Byte, High
Byte
(TBLPTRU:TBLPTRH:TBLPTRL) join to form a 22-bit
wide pointer. The lower 21-bits allow the device to
address up to 2 Mbytes of program memory space. The
22nd bit allows access to the Device ID, the User ID
and the Configuration bits.
The Table Pointer, TBLPTR, is used by the TBLRD and
TBLWT instructions. These instructions can update the
TBLPTR in one of four ways, based on the table operation.
These operations are shown in Table 5-1. These opera-
tions on the TBLPTR only affect the lower 21-bits.
When a Table Write occurs to an even program mem-
ory address (TBLPTR<0> = 0), the contents of TABLAT
are transferred to an internal holding register. This is
performed as a short write and the program memory
block is not actually programmed at this time. The hold-
ing register is not accessible by the user.
When a Table Write occurs to an odd program memory
address (TBLPTR<0>=1), a long write is started. Dur-
ing the long write, the contents of TABLAT are written
to the high byte of the program memory block and the
contents of the holding register are transferred to the
low byte of the program memory block.
Figure 5-3 shows the holding register and the program
memory write blocks.
If a single byte is to be programmed, the low (even)
byte of the destination program word should be read
using TBLRD*, modified or changed, if required, and
written back to the same address using TBLWT*+. The
high (odd) byte should be read using TBLRD*, modified
or changed if required, and written back to the same
address using TBLWT. A write to the odd address will
cause a long write to begin. This process ensures that
existing data in either byte will not be changed unless
desired.
and
TBLPTR - TABLE POINTER
REGISTER
Low
Byte).
PIC18CXX2
These
DS39026C-page 57
three
registers