PIC18C658-I/PT Microchip Technology, PIC18C658-I/PT Datasheet - Page 218
![32 KB OTP, 1536 RAM, 52 I/O 64 TQFP 10x10x1mm TRAY](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18C658-I/PT
Manufacturer Part Number
PIC18C658-I/PT
Description
32 KB OTP, 1536 RAM, 52 I/O 64 TQFP 10x10x1mm TRAY
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C770-ISO.pdf
(8 pages)
3.PIC18C658-IPT.pdf
(366 pages)
4.PIC18C658-IPT.pdf
(16 pages)
5.PIC18C658-IPT.pdf
(16 pages)
6.PIC18C658-IPT.pdf
(16 pages)
Specifications of PIC18C658-I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Processor Series
PIC18C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1536 B
Interface Type
3-Wire, I2C, SPI, USART, CAN
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
52
Number Of Timers
4 bit
Operating Supply Voltage
2.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
ICE2000, DM163007, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
6
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
PIC18C658I/PT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18C658-I/PT
Manufacturer:
Microchip
Quantity:
601
Company:
Part Number:
PIC18C658-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC16C770-ISO PDF datasheet #2
- PIC18C658-IPT PDF datasheet #3
- PIC18C658-IPT PDF datasheet #4
- PIC18C658-IPT PDF datasheet #5
- PIC18C658-IPT PDF datasheet #6
- Current page: 218 of 366
- Download datasheet (7Mb)
PIC18CXX8
17.7
All nodes on a given CAN bus must have the same
nominal
Non-Return-to-Zero (NRZ) coding, which does not
encode a clock within the data stream. Therefore, the
receive clock must be recovered by the receiving
nodes and synchronized to the transmitters clock.
As oscillators and transmission time may vary from
node to node, the receiver must have some type of
Phase Lock Loop (PLL) synchronized to data transmis-
sion edges, to synchronize and maintain the receiver
clock. Since the data is NRZ coded, it is necessary to
include bit stuffing to ensure that an edge occurs at
least every six bit times, to maintain the Digital Phase
Lock Loop (DPLL) synchronization.
The bit timing of the PIC18CXX8 is implemented using
a DPLL that is configured to synchronize to the incom-
ing data, and provide the nominal timing for the trans-
mitted data. The DPLL breaks each bit time into
multiple segments, made up of minimal periods of time
called the time quanta (T
Bus timing functions executed within the bit time frame,
such as synchronization to the local oscillator, network
transmission delay compensation, and sample point
positioning, are defined by the programmable bit timing
logic of the DPLL.
FIGURE 17-6: BIT TIME PARTITIONING
DS30475A-page 218
Input Signal
T
Baud Rate Setting
Q
bit
rate.
Sync
The
Q
).
CAN
Segment
Prop
protocol
Advanced Information
uses
Segment 1
Phase
Sample Point
All devices on the CAN bus must use the same bit rate.
However, all devices are not required to have the same
master oscillator clock frequency. For the different
clock frequencies of the individual devices, the bit rate
has to be adjusted by appropriately setting the baud
rate prescaler and number of time quanta in each seg-
ment.
The nominal bit rate is the number of bits transmitted
per second assuming an ideal transmitter with an ideal
oscillator, in the absence of resynchronization. The
nominal bit rate is defined to be a maximum of 1Mb/s.
Nominal Bit Time is defined as:
The nominal bit time can be thought of as being divided
into separate non-overlapping time segments. These
segments are shown in Figure 17-6.
• Synchronization Segment (Sync_Seg)
• Propagation Time Segment (Prop_Seg)
• Phase Buffer Segment 1 (Phase_Seg1)
• Phase Buffer Segment 2 [Phase_Seg2)
Nominal Bit Time = T
Phase_Seg1 + Phase_Seg2)
The time segments and also, the nominal bit time, are
made up of integer units of time called time quanta or
T
is programmable from a minimum of 8 T
mum of 25 T
bit time is 1 s, corresponding to a maximum 1 Mb/s
rate.
Q
(see Figure 17-6). By definition, the nominal bit time
T
BIT
= 1 / NOMlNAL BlT RATE
Q
. Also by definition, the minimum nominal
Q
Segment 2
* (Sync_Seg + Prop_Seg +
2000 Microchip Technology Inc.
Phase
Q
to a maxi-
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