PIC18F2221-E/SS Microchip Technology, PIC18F2221-E/SS Datasheet - Page 33

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PIC18F2221-E/SS

Manufacturer Part Number
PIC18F2221-E/SS
Description
4KB, Flash, 512bytes-RAM, 25I/O, 8-bit Family,nanoWatt 28 SSOP .209in TUBE
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F2221-E/SS

Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
3.6.4
The 4x Phase Locked Loop (PLL) can be used with the
internal oscillator block to produce faster device clock
speeds than are normally possible with the internal
oscillator sources. When enabled, the PLL produces a
clock speed of 16 MHz or 32 MHz.
Unlike HSPLL mode, the PLL is controlled through
software. The control bit, PLLEN (OSCTUNE<6>), is
used to enable or disable its operation. If PLL is
enabled and a Two-Speed Start-up from wake is
performed, execution is delayed until the PLL starts.
The PLL is available when the device is configured to
use the internal oscillator block as its primary clock
source (FOSC<3:0> = 1001 or 1000). Additionally, the
PLL will only function when the selected output fre-
quency is either 4 MHz or 8 MHz (OSCCON<6:4> = 111
or 110). If both of these conditions are not met, the PLL
is disabled and the PLLEN bit remains clear (writes are
ignored).
REGISTER 3-1:
© 2009 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4-0
PLL IN INTOSC MODES
OSCTUNE: OSCILLATOR TUNING REGISTER
PIC18F2221/2321/4221/4321 FAMILY
INTSRC: Internal Oscillator Low-Frequency Source Select bit
1 = 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled)
0 = 31 kHz device clock derived directly from INTRC internal oscillator
PLLEN: Frequency Multiplier PLL for INTOSC Enable bit
1 = PLL enabled for INTOSC (4 MHz and 8 MHz only)
0 = PLL disabled
Unimplemented: Read as ‘0’
TUN<4:0>: Frequency Tuning bits
01111 = Maximum frequency
00001
00000 = Center frequency. Oscillator module is running at the calibrated frequency.
11111
10000 = Minimum frequency
bit 7
Legend:
R = Readable bit
-n = Value at POR
INTSRC
R/W-0
Note 1: Available only in certain oscillator configurations; otherwise, this bit is unavailable
and reads as ‘0’. See Section 3.6.4 “PLL in INTOSC Modes” for details.
PLLEN
R/W-0
(1)
U-0
W = Writable bit
‘1’ = Bit is set
R/W-0
TUN4
3.6.5
The factory calibrates the internal oscillator block
output (INTOSC) for 8 MHz. However, this frequency
may drift as V
affect the controller operation in a variety of ways. It is
possible to adjust the INTOSC frequency by modifying
the value in the OSCTUNE register. This has no effect
on the INTRC clock source frequency.
Tuning the INTOSC source requires knowing when to
make the adjustment, in which direction it should be
made and in some cases, how large a change is
needed. Three compensation techniques are discussed
in
EUSART”, Section 3.6.5.2 “Compensating with the
Timers” and Section 3.6.5.3 “Compensating with the
CCP Module in Capture Mode” but other techniques
may be used.
Section 3.6.5.1
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
TUN3
INTOSC FREQUENCY DRIFT
DD
(1)
or temperature changes and can
R/W-0
TUN2
“Compensating
x = Bit is unknown
R/W-0
TUN1
DS39689F-page 33
with
R/W-0
TUN0
bit 0
the

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