PIC18F2480-E/SP Microchip Technology, PIC18F2480-E/SP Datasheet - Page 10
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18F2480-E/SP
Manufacturer Part Number
PIC18F2480-E/SP
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,DIP,28PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18F4480-IPT.pdf
(490 pages)
4.PIC18F4480-IPT.pdf
(8 pages)
5.PIC18F4480-IPT.pdf
(6 pages)
6.PIC18F4480-IPT.pdf
(6 pages)
7.PIC18LF2480-ISP.pdf
(14 pages)
Specifications of PIC18F2480-E/SP
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
PIC18F2480/2580/4480/4580
11. Module: ECAN Technology
12. Module: 10-Bit Analog-to-Digital
DS80496C-page 10
In Listen Only mode, the module may
persistently set the IRXIF and RXB0IF interrupt
flags, and the RXFUL status flag, after receiving
129 or more consecutive error frames. In this
case, the flags can be cleared, but then will
become set again immediately and continuously
without receiving a bus message.
Work around
Place the ECAN module in Configuration mode
before receiving 129 consecutive error frames
and then place it back into Listen Only mode.
Affected Silicon Revisions
When the AD clock source is selected as 2 T
or RC (when ADCS<2:0> = 000 or x11), in
extremely rare cases, the E
Error) and E
exceed the data sheet specifications at codes,
511 and 512 only.
Work around
Select the AD clock source as 4 T
16 T
2 T
Affected Silicon Revisions
A1
A1
X
X
OSC
OSC
or RC.
B0
B0
, 32 T
Converter
DL
OSC
B2
B2
(Differential Linearity Error) may
or 64 T
OSC
IL
and avoid selecting
(Integral Linearity
OSC
, 8 T
OSC
OSC
,
13. Module: MSSP
In SPI mode, the SDO output may change after
the inactive clock edge of the Bit 0 output. This
may affect some SPI components that read data
over 300 ns after the inactive edge of SCK.
Work around
None.
Affected Silicon Revisions
A1
X
B0
B2
2010 Microchip Technology Inc.