PIC18F2515-I/SO Microchip Technology, PIC18F2515-I/SO Datasheet
PIC18F2515-I/SO
Specifications of PIC18F2515-I/SO
Available stocks
Related parts for PIC18F2515-I/SO
PIC18F2515-I/SO Summary of contents
Page 1
... PIC18F2515/2610/4515/4610 Rev. A3 Silicon Errata The PIC18F2515/2610/4515/4610 Rev. A3 parts you have received conform functionally to the Device Data Sheet (DS39636C), except for described below. Any Data Sheet Clarification issues related to the PIC18F2515/2610/4515/4610 will be reported in a separate Data Sheet errata. Please check the Microchip web site for any existing issues. ...
Page 2
... PIC18F2515/2610/4515/4610 2. Module: MSSP When the MSSP is configured for SPI Master mode, the SDO pin cannot be disabled by setting the TRISC<5> bit. The SDO pin always outputs the content of SSPBUF regardless of the state of the TRIS bit. Work around Use Rev. A4 silicon devices. Date Codes that pertain to this issue: All engineering and production devices ...
Page 3
... DD Date Codes that pertain to this issue: All engineering and production devices. © 2007 Microchip Technology Inc. PIC18F2515/2610/4515/4610 9. Module: A/D The A/D offset is greater than the specified limit in Table 25-24 of the Device Data Sheet. The updated conditions and limits are shown in bold text in Table 2 ...
Page 4
... PIC18F2515/2610/4515/4610 12. Module: ECCP When the shutdown state of the PWM pin(s) is configured to tri-state the outputs, the device may consume higher than expected current during the shutdown event. Work around Configure the PWM output for either a high or low logic state during the shutdown PSSAC1:PSSAC0 (ECCP1AS< ...
Page 5
... TMRxL and TMRxH. Date Codes that pertain to this issue: All engineering and production devices. © 2007 Microchip Technology Inc. PIC18F2515/2610/4515/4610 20. Module: Timer1/Timer3 When Timer1 or Timer3 is in External Clock Synchronized mode and the external clock period is between 1 and 2 T ...
Page 6
... PIC18F2515/2610/4515/4610 23. Module: Interrupts If an interrupt occurs during a two-cycle instruction that modifies the STATUS, BSR or WREG register, the unmodified value of the register will be saved to the corresponding Fast Return (Shadow) register and upon a fast return from the interrupt, the unmodified value will be restored to the STATUS, BSR or WREG register ...
Page 7
... LowVector (void) { _asm goto MyLowISR _endasm } #pragma code /* return to default code section */ © 2007 Microchip Technology Inc. PIC18F2515/2610/4515/4610 then the interrupt is treated as high priority in spite directive. The code segment shown in Example 3 ® C18 C Com- demonstrates the work around using the C18 ...
Page 8
... PIC18F2515/2610/4515/4610 An optimized C18 version is also provided in Example 4. This example illustrates how it reduces the instruction cycle count from 10 cycles to 3: EXAMPLE 4: #pragma code high_vector_section=0x8 void high_vector (void) { _asm CALL high_vector_branch, 1 _endasm } void high_vector_branch (void) { _asm POP GOTO high_isr _endasm } #pragma interrupt high_isr ...
Page 9
... Work around Use pull-up resistor on TX pin. Date Codes that pertain to this issue: All engineering and production devices. © 2007 Microchip Technology Inc. PIC18F2515/2610/4515/4610 28. Module: MSSP system with multiple slave nodes, an unaddressed slave may respond to bus activity when data on the bus matches its address. The first occurrence will set the BF bit ...
Page 10
... PIC18F2515/2610/4515/4610 31. Module: MSSP Setting the SEN bit initiates a Start sequence on the bus, after which, the SEN bit is cleared auto- matically by hardware. If the SEN bit is set again (without an address byte being transmitted), a Start sequence will not commence and the SEN bit will not be cleared. This condition causes the bus to remain in an active state ...
Page 11
... TXREG when timer is about to overflow. Date Codes that pertain to this issue: All engineering and production devices. © 2007 Microchip Technology Inc. PIC18F2515/2610/4515/4610 35. Module: EUSART In 9-Bit Asynchronous Full-Duplex Receive mode, the received data may be corrupted if the TX9D bit (TXSTA<0>) is not modified immediately after the RCIDL bit (BAUDCON< ...
Page 12
... PIC18F2515/2610/4515/4610 38. Module: Timer1 In 16-Bit Asynchronous Counter mode (with or without use of the Timer1 oscillator), the TMR1H and TMR3H buffers do not update when TMRxL is read. This issue only affects reading the TMRxH regis- ters. The timers increments and set the interrupt flags as expected. The timer registers can also be written as expected ...
Page 13
... Q4 cycle). Work around None Date Codes that pertain to this issue: All engineering and production devices. © 2007 Microchip Technology Inc. PIC18F2515/2610/4515/4610 44. Module: 10-Bit Analog-to-Digital (A/D) Converter Module When the A/D clock source is selected (when ADCS2:ADCS0 = 000 or x11), in extremely rare cases, the E ...
Page 14
... PIC18F2515/2610/4515/4610 REVISION HISTORY Rev A Document (8/2004) First revision of this document. Issues 1-4 (MSSP), 5-7 (ECCP), 8 (ECCP and CCP), 9 A/D, and 10 (DC Characteristics). Data Sheet Clarification issues 1 (I/O Ports) and 2 (Resets). Rev B Document (2/2005) Added Date Code information to all issues, updated text and reordered issues for clarity. ...
Page 15
... PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
Page 16
... Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2007 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...