PIC18F4585-E/ML Microchip Technology, PIC18F4585-E/ML Datasheet - Page 3

• Manufacturer Part Number: PIC18F4585-E/ML
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,44PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4585-E/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-QFN
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: I2C, SPI, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 44
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11 bit
• Height: 0.88 mm
• Length: 8 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.2 V
• Width: 8 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3-DB18F4680 - BOARD DAUGHTER ICEPIC3
• Lead Free Status / Rohs Status: Details

11. Module: MSSP
12. Module: MSSP
TABLE 1:
© 2007 Microchip Technology Inc.
Note 1:
When the MSSP is configured for SPI Master
mode, the SDO pin cannot be disabled by setting
the TRISC<5> bit. The SDO pin always outputs
the content of SSPBUF regardless of the state of
the TRIS bit.
In Slave mode with slave select enabled,
SSPM3:SSPM0 = 0010 (SSPCON1<3:0>), the
SDO pin can be disabled by placing a logic high
level on the SS pin (RA5).
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices
After an I
register may be written for up to 10 T
additional writes are blocked. The data transfer
may be corrupted if SSPBUF is written to during
this time.
The WCOL bit is set anytime an SSPBUF write
occurs during a transfer.
40 MHz
40 MHz
40 MHz
16 MHz
16 MHz
16 MHz
4 MHz
4 MHz
4 MHz
F
OSC
The I
100 kHz) in all details, but may be used with care where higher rates are required by the application.
2
C™ transfer is initiated, the SSPBUF
I
2
2
C™ interface does not conform to the 400 kHz I
C™ CLOCK RATE w/BRG
10 MHz
10 MHz
10 MHz
4 MHz
4 MHz
4 MHz
1 MHz
1 MHz
1 MHz
F
CY
CY
PIC18F2585/2680/4585/4680
before
20 MHz
20 MHz
20 MHz
F
8 MHz
8 MHz
8 MHz
2 MHz
2 MHz
2 MHz
CY
* 2
13. Module: MSSP
2
C specification (which applies to rates greater than
Work around
Avoid writing SSPBUF until the data transfer is
complete, indicated by the setting of the SSPIF bit
(PIR1<3>).
Verify the WCOL bit (SSPCON1<7>) is clear after
writing SSPBUF to ensure any potential transfer in
progress is not corrupted.
Date Codes that pertain to this issue:
All engineering and production devices.
In its current implementation, the I
operates as follows:
1. The Baud Rate Generator for I
2. Use the following formula in place of the one
mode is slower than the rates specified in
Table 17-3 of the Device Data Sheet.
For this revision of silicon, use the values
shown in Table 1 in place of those shown in
Table 17-3 of the Device Data Sheet. The
differences are shown in bold text.
shown in Register 17-4 (SSPCON1) of the
Device
SSPM3:SSPM0 = 1000.
SSPADD = INT((F
BRG Value
0Eh
15h
59h
05h
08h
23h
01h
08h
00h
Data
Sheet
CY
/F
SCL
(2 Rollovers of BRG)
) – (F
for
CY
400 kHz
400 kHz
333 kHz
312.5 kHz
DS80202G-page 3
2
bit
1 MHz
100 kHz
308 kHz
100 kHz
100 kHz
C Master mode
/1.111 MHz)) – 1
F
2
SCL
C in Master
description,
(1)
(1)
(1)
(1)