PIC18F8621-E/PT Microchip Technology, PIC18F8621-E/PT Datasheet - Page 291
PIC18F8621-E/PT
Manufacturer Part Number
PIC18F8621-E/PT
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,80PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F6525-IPT.pdf
(396 pages)
3.PIC18F6525-IPT.pdf
(8 pages)
4.PIC18F6525-IPT.pdf
(38 pages)
Specifications of PIC18F8621-E/PT
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.75K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
80-TFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F8621-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18F6525-IPT PDF datasheet #2
- PIC18F6525-IPT PDF datasheet #3
- PIC18F6525-IPT PDF datasheet #4
- Current page: 291 of 396
- Download datasheet (8Mb)
BTG
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
2005 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction:
After Instruction:
Decode
PORTC =
PORTC =
Q1
register ‘f’
Bit Toggle f
[ label ] BTG f,b[,a]
0 ≤ f ≤ 255
0 ≤ b < 7
a ∈ [0,1]
(f<b>) → f<b>
None
Bit ‘b’ in data memory location ‘f’ is
inverted. If ‘a’ is ‘0’, the Access Bank will
be selected, overriding the BSR value. If
‘a’ = 1, then the bank will be selected as
per the BSR value (default).
1
1
BTG
Read
0111
Q2
0111 0101 [0x75]
0110 0101 [0x65]
PORTC,
bbba
Process
Data
Q3
4, 0
ffff
register ‘f’
PIC18F6525/6621/8525/8621
Write
Q4
ffff
BOV
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
No
PC
If Overflow
If Overflow
Q1
Q1
PC
PC
Read literal
Read literal
operation
Branch if Overflow
[ label ] BOV
-128 ≤ n ≤ 127
if Overflow bit is ‘1’
None
If the Overflow bit is ‘1’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
HERE
1110
(PC) + 2 + 2n → PC
No
Q2
‘n’
Q2
‘n’
=
=
=
=
=
address (HERE)
1;
address (Jump)
0;
address (HERE + 2)
0100
BOV
operation
Process
Process
n
Data
Data
No
Q3
Q3
DS39612B-page 289
Jump
nnnn
Write to PC
operation
operation
No
No
Q4
Q4
nnnn
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