PIC18F8621-E/PT Microchip Technology, PIC18F8621-E/PT Datasheet - Page 24
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PIC18F8621-E/PT
Manufacturer Part Number
PIC18F8621-E/PT
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,80PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F6525-IPT.pdf
(396 pages)
3.PIC18F6525-IPT.pdf
(8 pages)
4.PIC18F6525-IPT.pdf
(38 pages)
Specifications of PIC18F8621-E/PT
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.75K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
80-TFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F8621-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC18F6X2X/8X2X
4.3
A configuration address may be read and output on
PGD via the 4-bit command, ‘1001’. Configuration data
is read and written in a byte-wise fashion, so it is not
necessary to merge two bytes into a word prior to a
compare.
pared to the appropriate configuration data in the pro-
grammer’s
Section 4.1 for implementation details of reading
configuration data.
4.4
Data EEPROM is accessed one byte at a time via an
address pointer (register pair EEADR:EEADRH) and a
data latch (EEDATA). Data EEPROM is read by loading
EEADR:EEADRH with the desired memory location
and initiating a memory read by appropriately configur-
ing the EECON1 register. The data will be loaded into
EEDATA, where it may be serially output on PGD via
the 4-bit command, ‘0010’ (Shift Out Data Holding reg-
ister). A delay of P6 must be introduced after the falling
edge of the 8th PGC of the operand to allow PGD to
transition from an input to an output. During this time,
PGC must be held low (see Figure 4-4).
The command sequence to read a single byte of data
is shown in Table 4-2.
TABLE 4-2:
DS30499B-page 24
Step 1: Direct access to data EEPROM.
Step 2: Set the data EEPROM address pointer.
Step 3: Initiate a memory read.
Step 4: Load data into the Serial Data Holding register.
Note 1:
Command
0000
0000
0000
0000
0000
0000
0000
0000
0000
0010
4-bit
Verify Configuration Bits
Read Data EEPROM Memory
The <LSB> is undefined. The <MSB> is the data.
The result may then be immediately com-
memory
9E A6
9C A6
0E <Addr>
6E A9
OE <AddrH>
6E AA
80 A6
50 A8
6E F5
<LSB><MSB>
READ DATA EEPROM MEMORY
Data Payload
for
verification.
BCF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
MOVF
MOVWF
Shift Out Data
Refer
EECON1, EEPGD
EECON1, CFGS
<Addr>
EEADR
<AddrH>
EEADRH
EECON1, RD
EEDATA, W, 0
TABLAT
to
(1)
FIGURE 4-3:
Core Instruction
No
Move to TABLAT
READ DATA EEPROM
FLOW
Shift Out Data
2003 Microchip Technology Inc.
Address
Read
Done
Byte
Start
Done
Set
?
Yes