PIC18LF24J10-I/SO Microchip Technology, PIC18LF24J10-I/SO Datasheet - Page 22
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PIC18LF24J10-I/SO
Manufacturer Part Number
PIC18LF24J10-I/SO
Description
Microcontroller
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F24J10-ISO.pdf
(368 pages)
3.PIC18F24J10-ISO.pdf
(6 pages)
4.PIC18F24J10-ISO.pdf
(6 pages)
5.PIC18F24J10-ISO.pdf
(12 pages)
6.PIC18LF24J10-ISS.pdf
(32 pages)
Specifications of PIC18LF24J10-I/SO
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPIC, I2C, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180012 - MODULE PLUG-IN 18LF25J10 28SOICAC162067 - HEADER INTRFC MPLAB ICD2 40/28PAC164332 - MODULE SKT FOR 28SOIC 18F45J10
Eeprom Size
-
Lead Free Status / Rohs Status
Details
- PIC16F616T-ISL PDF datasheet
- PIC18F24J10-ISO PDF datasheet #2
- PIC18F24J10-ISO PDF datasheet #3
- PIC18F24J10-ISO PDF datasheet #4
- PIC18F24J10-ISO PDF datasheet #5
- PIC18LF24J10-ISS PDF datasheet #6
- Current page: 22 of 368
- Download datasheet (6Mb)
PIC18F45J10 FAMILY
TABLE 1-3:
DS39682E-page 20
RD0/PSP0/SCK2/
SCL2
RD1/PSP1/SDI2/SDA2
RD2/PSP2/SDO2
RD3/PSP3/SS2
RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
Legend: TTL = TTL compatible input
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
RD0
PSP0
SCK2
SCL2
RD1
PSP1
SDI2
SDA2
RD2
PSP2
SDO2
RD3
PSP3
SS2
RD4
PSP4
RD5
PSP5
P1B
RD6
PSP6
P1C
RD7
PSP7
P1D
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
Pin Name
ST = Schmitt Trigger input with CMOS levels
O
= Output
PIC18F44J10/45J10 PINOUT I/O DESCRIPTIONS (CONTINUED)
PDIP
19
20
21
22
27
28
29
30
Pin Number
QFN TQFP
38
39
40
41
2
3
4
5
38
39
40
41
2
3
4
5
Type
Pin
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
I
I
Buffer
Type
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
—
—
—
—
CMOS = CMOS compatible input or output
I
P
PORTD is a bidirectional I/O port or a Parallel Slave
Port (PSP) for interfacing to a microprocessor port.
These pins have TTL input buffers when PSP module
is enabled.
Digital I/O.
Parallel Slave Port data.
Synchronous serial clock input/output for
SPI mode.
Synchronous serial clock input/output for
I
Digital I/O.
Parallel Slave Port data.
SPI data in.
I
Digital I/O.
Parallel Slave Port data.
SPI data out.
Digital I/O.
Parallel Slave Port data.
SPI slave select input.
Digital I/O.
Parallel Slave Port data.
Digital I/O.
Parallel Slave Port data.
Enhanced CCP1 output.
Digital I/O.
Parallel Slave Port data.
Enhanced CCP1 output.
Digital I/O.
Parallel Slave Port data.
Enhanced CCP1 output.
2
2
C™ mode.
C data I/O.
= Input
= Power
Description
© 2009 Microchip Technology Inc.
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