PIC18LF24J10-I/SO Microchip Technology, PIC18LF24J10-I/SO Datasheet - Page 42
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PIC18LF24J10-I/SO
Manufacturer Part Number
PIC18LF24J10-I/SO
Description
Microcontroller
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F24J10-ISO.pdf
(368 pages)
3.PIC18F24J10-ISO.pdf
(6 pages)
4.PIC18F24J10-ISO.pdf
(6 pages)
5.PIC18F24J10-ISO.pdf
(12 pages)
6.PIC18LF24J10-ISS.pdf
(32 pages)
Specifications of PIC18LF24J10-I/SO
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPIC, I2C, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180012 - MODULE PLUG-IN 18LF25J10 28SOICAC162067 - HEADER INTRFC MPLAB ICD2 40/28PAC164332 - MODULE SKT FOR 28SOIC 18F45J10
Eeprom Size
-
Lead Free Status / Rohs Status
Details
- PIC16F616T-ISL PDF datasheet
- PIC18F24J10-ISO PDF datasheet #2
- PIC18F24J10-ISO PDF datasheet #3
- PIC18F24J10-ISO PDF datasheet #4
- PIC18F24J10-ISO PDF datasheet #5
- PIC18LF24J10-ISS PDF datasheet #6
- Current page: 42 of 368
- Download datasheet (6Mb)
PIC18F45J10 FAMILY
4.4.3
In RC_IDLE mode, the CPU is disabled but the periph-
erals continue to be clocked from the internal oscillator.
This mode allows for controllable power conservation
during Idle periods.
From RC_RUN, this mode is entered by setting the
IDLEN bit and executing a SLEEP instruction. If the
device is in another Run mode, first set IDLEN, then
clear the SCS bits and execute SLEEP. When the clock
source is switched to the INTRC, the primary oscillator
is shut down and the OSTS bit is cleared.
When a wake event occurs, the peripherals continue to
be clocked from the INTRC. After a delay of T
following the wake event, the CPU begins executing
code being clocked by the INTRC. The IDLEN and
SCS bits are not affected by the wake-up. The INTRC
source will continue to run if either the WDT or the
Fail-Safe Clock Monitor is enabled.
4.5
An exit from Sleep mode, or any of the Idle modes, is
triggered by an interrupt, a Reset or a WDT time-out.
This section discusses the triggers that cause exits
from power-managed modes. The clocking subsystem
actions are discussed in each of the power-managed
modes sections (see Section 4.2 “Run Modes”,
Section 4.3 “Sleep Mode” and Section 4.4 “Idle
Modes”).
4.5.1
Any of the available interrupt sources can cause the
device to exit from an Idle mode, or the Sleep mode, to
a Run mode. To enable this functionality, an interrupt
source must be enabled by setting its enable bit in one
of the INTCON or PIE registers. The exit sequence is
initiated when the corresponding interrupt flag bit is set.
On all exits from Idle or Sleep modes by interrupt, code
execution branches to the interrupt vector if the
GIE/GIEH bit (INTCON<7>) is set. Otherwise, code
execution continues or resumes without branching
(see Section 9.0 “Interrupts”).
A fixed delay of interval, T
is required when leaving Sleep and Idle modes. This
delay is required for the CPU to prepare for execution.
Instruction execution resumes on the first clock cycle
following this delay.
DS39682E-page 40
Exiting Idle and Sleep Modes
RC_IDLE MODE
EXIT BY INTERRUPT
CSD
, following the wake event
CSD
4.5.2
A WDT time-out will cause different actions depending
on which power-managed mode the device is in when
the time-out occurs.
If the device is not executing code (all Idle modes and
Sleep mode), the time-out will result in an exit from the
power-managed
Modes” and Section 4.3 “Sleep Mode”). If the device
is executing code (all Run modes), the time-out will
result in a WDT Reset (see Section 21.2 “Watchdog
Timer (WDT)”).
The WDT timer and postscaler are cleared by one of
the following events:
• executing a SLEEP or CLRWDT instruction
• the loss of a currently selected clock source (if the
4.5.3
Exiting an Idle or Sleep mode by Reset automatically
forces the device to run from the INTRC.
4.5.4
Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:
• PRI_IDLE mode where the primary clock source
• the primary clock source is the EC mode.
In these instances, the primary clock source either
does not require an oscillator start-up delay, since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (EC). However, a
fixed delay of interval, T
is still required when leaving Sleep and Idle modes to
allow the CPU to prepare for execution. Instruction
execution resumes on the first clock cycle following this
delay.
Fail-Safe Clock Monitor is enabled)
is not stopped; and
EXIT BY WDT TIME-OUT
EXIT BY RESET
EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
mode
© 2009 Microchip Technology Inc.
CSD
(see
, following the wake event
Section 4.2
“Run
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