PIC18LF24J10-I/SS Microchip Technology, PIC18LF24J10-I/SS Datasheet - Page 328
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PIC18LF24J10-I/SS
Manufacturer Part Number
PIC18LF24J10-I/SS
Description
Microcontroller
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F24J10-ISO.pdf
(368 pages)
3.PIC18F24J10-ISO.pdf
(6 pages)
4.PIC18F24J10-ISO.pdf
(6 pages)
5.PIC18F24J10-ISO.pdf
(12 pages)
6.PIC18LF24J10-ISS.pdf
(32 pages)
Specifications of PIC18LF24J10-I/SS
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPIC, I2C, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180012 - MODULE PLUG-IN 18LF25J10 28SOICAC162067 - HEADER INTRFC MPLAB ICD2 40/28PAC164331 - MODULE SKT FOR 28SSOP 18F45J10XLT28SS-1 - SOCKET TRANSITION ICE 28SSOP
Eeprom Size
-
Lead Free Status / Rohs Status
Details
- PIC16F616T-ISL PDF datasheet
- PIC18F24J10-ISO PDF datasheet #2
- PIC18F24J10-ISO PDF datasheet #3
- PIC18F24J10-ISO PDF datasheet #4
- PIC18F24J10-ISO PDF datasheet #5
- PIC18LF24J10-ISS PDF datasheet #6
- Current page: 328 of 368
- Download datasheet (6Mb)
PIC18F45J10 FAMILY
FIGURE 24-11:
TABLE 24-15: EXAMPLE SPI™ MODE REQUIREMENTS (CKE = 1)
DS39682E-page 326
73
73A
74
75
76
78
79
80
81
Note 1:
Param.
No.
Note:
SSx
SCKx
(CKP = 0)
SCKx
(CKP = 1)
SDOx
SDIx
T
T
T
T
T
T
T
T
T
T
T
T
T
SC
SC
SC
SC
SC
SC
DI
DI
B
DO
DO
DO
DO
Only if Parameter #71A and #72A are used.
Symbol
Refer to Figure 24-3 for load conditions.
2
V2
V2
H2
L2
R
F
H2
L2
B
R
F
V2
V2
SC
SC
DI
DO
DI
DO
SC
SC
L
L,
H,
L
V
V,
H,
L
EXAMPLE SPI™ MASTER MODE TIMING (CKE = 1)
Setup Time of SDIx Data Input to SCKx Edge
Last Clock Edge of Byte 1 to the 1st Clock Edge
of Byte 2
Hold Time of SDIx Data Input to SCKx Edge
SDOx Data Output Rise Time
SDOx Data Output Fall Time
SCKx Output Rise Time (Master mode)
SCKx Output Fall Time (Master mode)
SDOx Data Output Valid after SCKx Edge
SDOx Data Output Setup to SCKx Edge
81
73
MSb In
MSb
74
71
Characteristic
75, 76
80
72
bit 6 - - - - - - 1
bit 6 - - - - 1
LSb In
LSb
1.5 T
Min
T
20
CY
40
—
—
—
—
—
CY
79
78
+ 40
© 2009 Microchip Technology Inc.
Max Units
25
25
25
50
—
—
25
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note 1)
Conditions
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