PIC18LF2550T-I/SO Microchip Technology, PIC18LF2550T-I/SO Datasheet - Page 14
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PIC18LF2550T-I/SO
Manufacturer Part Number
PIC18LF2550T-I/SO
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,28PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PCM18XR1.pdf
(438 pages)
3.PIC18F2221-ISO.pdf
(46 pages)
4.PIC18F2455-ISO.pdf
(14 pages)
5.PIC18F2455-ISO.pdf
(8 pages)
6.PIC18F2455-ISO.pdf
(26 pages)
Specifications of PIC18LF2550T-I/SO
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SPI, I2C, EAUSART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
24
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163025, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
PIC18F2455/2550/4455/4550
31. Module: MSSP
TABLE 3:
DS80478A-page 14
Param
70
No.
When operated in I
baud rate may be somewhat slower than predicted
by the following formula:
Work around
If the target application is sensitive to the baud rate
and requires more precision, the SSPADD value
can be adjusted to compensate.
If this work around is going to be used, it is recom-
mended that the firmware first check the Revision
ID by reading the DEVID1 value at address,
3FFFFEh. Silicon revisions, B6 and B7, will match
the I
Affected Silicon Revisions
I
A3
2
T
T
X
2
C Master mode, clock
SS
SS
Symbol
C baud rate predicted by the given formula.
L2
L2
SC
SC
EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING)
H,
L
B4
X
SS ↓ to SCK ↓ or SCK ↑ Input
2
C™ Master mode, the I
B5
X
=
--------------------------------------------- -
4
•
(
SSPADD
B6
F
OSC
Characteristic
+
B7
1
)
2
C
32. Module: MSSP
In SPI Slave mode with slave select enabled
(SSPM<3:0> = 0100), the minimum time between
the falling edge of the SS pin and first SCK edge
is greater than specified in parameter 70 in
Table 28-17 and Table 28-18. The updated
The minimum time between SS pin low and an
SSPBUF write is also 3 T
the SS pin occurs greater than 3 T
first SCK edge or loading SSPBUF, the peripheral
will function correctly. Also, if SSPBUF is written
prior to the SS pin going low, the peripheral will
function correctly.
Work around
None.
Affected Silicon Revisions
specification is shown in bold in Table 3.
A3
3 T
B4
Min
X
CY
© 2009 Microchip Technology Inc.
B5
Max Units Conditions
X
—
CY
. If the falling edge of
ns
B6
X
CY
, before the
B7
X