RFPIC12F675KT-I/SS Microchip Technology, RFPIC12F675KT-I/SS Datasheet - Page 21
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RFPIC12F675KT-I/SS
Manufacturer Part Number
RFPIC12F675KT-I/SS
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SSOP,20PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC®r
Specifications of RFPIC12F675KT-I/SS
Rohs Compliant
YES
Frequency
850MHz ~ 950MHz
Applications
RKE, Security Systems
Modulation Or Protocol
ASK, FSK
Data Rate - Maximum
40 kbps
Power - Output
10dBm
Current - Transmitting
14mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Memory Size
1024 x 14 words Flash, 128 x 8 Byte EEPROM, 64 x 8 Byte SRAM
Voltage - Supply
2V ~ 5.5V
Operating Temperature
-40°C ~ 125°C
Package / Case
20-SSOP
Processor Series
RFPIC12F
Core
PIC
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
1024 B
Data Ram Size
64 B
Interface Type
USB
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
6
Number Of Timers
2
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ICE2000, DV164102, AC164101, AC164103
Minimum Operating Temperature
- 40 C
On-chip Adc
4 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC164104 - MODULE RCVR RFPIC 315MHZAC164102 - MODULE TRANSMITTER RFPIC 315MHZAC124002 - MOD SKT PROMATEII 18SOIC/20SSOP
Features
-
Lead Free Status / Rohs Status
Details
Other names
RFPIC12F675KT-ISS
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
RFPIC12F675KT-I/SS
Manufacturer:
BOURNS
Quantity:
12 000
3.2.2
Each of the GPIO pins is individually configurable as an
interrupt-on-change pin. Control bits IOC enable or
disable the interrupt function for each pin. Refer to
Register 3-4. The interrupt-on-change is disabled on a
Power-on Reset.
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
GPIO. The ‘mismatch’ outputs of the last read are OR'd
together to set, the GP Port Change Interrupt flag bit
(GPIF) in the INTCON register.
REGISTER 3-4:
2003 Microchip Technology Inc.
bit 7-6
bit 5-0
INTERRUPT-ON-CHANGE
IOC — INTERRUPT-ON-CHANGE GPIO REGISTER (ADDRESS: 96h)
bit 7
Unimplemented: Read as ‘0’
IOC<5:0>: Interrupt-on-Change GPIO Control bit
1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
Note 1: Global interrupt enable (GIE) must be enabled for individual interrupts to be
Legend:
R = Readable bit
- n = Value at POR
U-0
—
recognized.
U-0
—
R/W-0
IOC5
Preliminary
W = Writable bit
’1’ = Bit is set
R/W-0
IOC4
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
b)
A mismatch condition will continue to set flag bit GPIF.
Reading GPIO will end the mismatch condition and
allow flag bit GPIF to be cleared.
Note:
Any read or write of GPIO. This will end the
mismatch condition.
Clear the flag bit GPIF.
R/W-0
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
IOC3
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the GPIF inter-
rupt flag may not get set.
R/W-0
IOC2
rfPIC12F675
x = Bit is unknown
R/W-0
IOC1
DS70091A-page 19
R/W-0
IOC0
bit 0