USBN9604-28MX National Semiconductor, USBN9604-28MX Datasheet - Page 4

• Manufacturer Part Number: USBN9604-28MX
• Description: IC,Bus Controller,SOP,28PIN
• Manufacturer: National Semiconductor

Specifications of USBN9604-28MX

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table of Contents
1.0
2.0
3.0
4.0
5.0
6.0
7.0
Signal/Pin Connection and Description
1.1
1.2
Functional Overview
2.1
2.2
2.3
2.4
2.5
Parallel Interface
3.1
3.2
Direct Memory Access (DMA) Support
4.1
4.2
MICROWIRE/PLUS Interface
5.1
5.2
Functional Description
6.1
6.2
6.3
6.4
Register Set
7.1
CONNECTION DIAGRAMS ........................................................................................................ 6
DETAILED SIGNAL/PIN DESCRIPTIONS .................................................................................. 7
1.2.1
1.2.2
1.2.3
1.2.4
TRANSCEIVER ......................................................................................................................... 10
VOLTAGE REGULATOR (VREG) ............................................................................................. 10
SERIAL INTERFACE ENGINE (SIE) ......................................................................................... 10
ENDPOINT PIPE CONTROLLER (EPC) ................................................................................... 12
MICROCONTROLLER INTERFACE ......................................................................................... 12
NON-MULTIPLEXED MODE ..................................................................................................... 13
3.1.1
3.1.2
3.1.3
MULTIPLEXED MODE .............................................................................................................. 15
STANDARD DMA MODE (DMA) ............................................................................................... 16
AUTOMATIC DMA MODE (ADMA) ........................................................................................... 17
OPERATING COMMANDS ....................................................................................................... 19
READ AND WRITE TIMING ...................................................................................................... 20
FUNCTIONAL STATES ............................................................................................................. 22
6.1.1
6.1.2
ENDPOINT OPERATION .......................................................................................................... 24
6.2.1
6.2.2
6.2.3
POWER SAVING MODES ........................................................................................................ 28
CLOCK GENERATION .............................................................................................................. 29
CONTROL REGISTERS ........................................................................................................... 30
7.1.1
Power Supply ................................................................................................................ 7
Oscillator, Clock and Reset ........................................................................................... 7
USB Port ....................................................................................................................... 8
Microprocessor Interface ............................................................................................... 8
Standard Access Mode ............................................................................................... 14
Burst Mode .................................................................................................................. 14
User Registers ............................................................................................................. 14
Line Condition Detection ............................................................................................. 22
Functional State Transition .......................................................................................... 22
Address Detection ....................................................................................................... 24
Transmit and Receive Endpoint FIFOs ....................................................................... 24
Programming Model .................................................................................................... 28
Main Control Register (MCNTRL) ............................................................................... 30
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