USBN9604-28MX/NOPB National Semiconductor, USBN9604-28MX/NOPB Datasheet - Page 31

• Manufacturer Part Number: USBN9604-28MX/NOPB
• Description: IC,Bus Controller,SOP,28PIN
• Manufacturer: National Semiconductor

Specifications of USBN9604-28MX/NOPB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.0 Register Set
7.1.2
CLKDIV
External Clock Divisor. The power-on reset and a hardware reset configure the divisor to 11
a 4 MHz output clock.
If the CLKDIV value is changed by firmware, the clock output is expanded/shortened if the CLKDIV value is increased/de-
creased in its current phase, to allow glitch-free switching at the CLKOUT pin.
CODIS
Clock Output Disable. Setting this bit disables the clock output. The CLKOUT output signal is frozen in its current state and
resumes with a new period when this bit is cleared.
7.1.3
This register holds the binary encoded chip revision.
REVID
Revision Identification. For revision 9603 Rev A and 9604 Rev A, the field contains 0010
Clock Configuration Register (CCONF)
Revision Identifier (RID)
frequency = 48 MHz / (CLKDIV+1)
CODIS
bit 7
bit 7
r/w
0
(Continued)
bit 6
bit 6
Reserved
-
-
Reserved
1
0
0
1
1
INTOC
Table 5. Interrupt Output Control Bits
bit 5
bit 5
-
-
0
0
1
0
1
Disabled
Active low open drain
Active high push-pull
Active low push-pull
bit 4
bit 4
31
Interrupt Output
bit 3
bit 3
1
0
bit 2
bit 2
0
0
CLKDIV3-0
REVID3-0
r/w
r
bit 1
bit 1
b
1
1
.
d
(decimal format), which yields
bit 0
bit 0
1
0
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