USBN9604-28MX/NOPB National Semiconductor, USBN9604-28MX/NOPB Datasheet - Page 44

• Manufacturer Part Number: USBN9604-28MX/NOPB
• Description: IC,Bus Controller,SOP,28PIN
• Manufacturer: National Semiconductor

Specifications of USBN9604-28MX/NOPB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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7.0 Register Set
7.2.15 Transmit Command 0 Register (TXC0)
TX_EN
Transmission Enable. This bit enables data transmission from the FIFO. It is cleared by the chip after transmitting a single
packet, or a STALL handshake, in response to an IN token. It must be set by firmware to start packet transmission. The
RX_EN bit in the Receive Command 0 (RXC0) register takes precedence over this bit; i.e. if RX_EN is set, TX_EN bit is
ignored until RX_EN is reset.
Zero length packets are indicated by setting this bit without writing any data to the FIFO.
TOGGLE
This bit specifies the PID used when transmitting the packet. A value of 0 causes a DATA0 PID to be generated, while a
value of 1 causes a DATA1 PID to be generated. This bit is not altered by the hardware.
FLUSH
Writing a 1 to this bit flushes all data from the control endpoint FIFOs, resets the endpoint to Idle state, clears the FIFO read
and write pointer, and then clears itself. If the endpoint is currently using the FIFO0 to transfer data on USB, flushing is de-
layed until after the transfer is done. This bit is cleared on reset. It is equivalent to the FLUSH bit in the RXC0 register.
IGN_IN
Ignore IN tokens. When this bit is set, the endpoint will ignore any IN tokens directed to its configured address.
7.2.16 Transmit Data 0 Register (TXD0)
.
TXFD
Transmit FIFO Data Byte. See “Bidirectional Control Endpoint FIFO0 Operation” in Section 6.2.2 for a description of data
handling.
The firmware is expected to write only the packet payload data. The PID and CRC16 are created automatically.
7.2.17 Receive Status 0 Register (RXS0)
This is the Receive Status register for the bidirectional Control Endpoint 0. To receive a SETUP packet after receiving a zero
length OUT/SETUP packet, there are two copies of this register in hardware. One holds the receive status of a zero length
packet, and another holds the status of the next SETUP packet with data. If a zero length packet is followed by a SETUP
packet, the first read of this register indicates the status of the zero length packet (with RX_LAST set to 1 and RCOUNT set
to 0) and the second read indicates the status of the SETUP packet.
RCOUNT
Receive Count. Indicates the count of bytes presently in the RX FIFO. This field is never larger than 8 for Endpoint 0.
Reserved
bit 7
bit 7
bit 7
-
-
(Continued)
Reserved
bit 6
-
-
bit 6
SETUP
CoR
bit 6
0
bit 5
bit 5
TOGGLE
bit 5
CoR
0
IGN_IN
bit 4
r/w
0
bit 4
RX_LAST
TXFD
FLUSH
r/w HW
r/w
44
bit 4
CoR
bit 3
-
0
0
bit 3
TOGGLE
bit 3
0
bit 2
r/w
0
bit 2
bit 2
RCOUNT3-0
0
Reserved
bit 1
bit 1
r
-
-
bit 1
0
r/w HW
TX_EN
bit 0
bit 0
bit 0
0
0