AS5013-ASST-1000 austriamicrosystems, AS5013-ASST-1000 Datasheet - Page 8

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AS5013-ASST-1000

Manufacturer Part Number
AS5013-ASST-1000
Description
IC ENCODER MAGNET 16-QFN
Manufacturer
austriamicrosystems
Series
EasyPoint™r
Type
Special Purposer
Datasheet

Specifications of AS5013-ASST-1000

Sensing Range
30mT ~ 120mT
Voltage - Supply
2.7 V ~ 3.6 V
Current - Supply
190µA
Output Type
Digital, Open Drain
Features
Low Power
Operating Temperature
-20°C ~ 80°C
Package / Case
16-UQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Output (max)
-
Other names
AS5013-ASST-1000TR
AS5013
Data Sheet
3.4 Xp Register (12h)
3.5 Xn Register (13h)
3.6 Yp Register (14h)
3.7 Yn Register (15h)
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Xp range value, 2’complement (signed: -128~+127).
Determines the RIGHT threshold for the activation of INTn output (if output enabled), when bit INT_function
= 1 (see Control Register 1(0Fh)).
Xn range value, 2’complement (signed: -128~+127).
Determines the LEFT threshold for the activation of INTn output (if output enabled), when bit INT_function =
1 (see Control Register 1 (0Fh)).
Yp range value, 2’complement (signed: -128~+127).
Determines the TOP threshold for the activation of INTn output (if output enabled), when bit INT_function =
1 (see Control Register (0Fh)).
Yn range value, 2’complement (signed: -128~+127).
Determines the BOTTOM threshold for the activation of INTn output (if output enabled), when bit
INT_function = 1 (see Control Register (0Fh)).
Reset value: 0000 0101 (5d)
Reset value: 1111 1011 (-5d)
Reset value: 0000 0101 (5d)
Reset value: 1111 1011 (-5d)
Xp [7]
Xn [7]
Yp [7]
Yn [7]
Bit 7
Bit 7
Bit 7
Bit 7
R/W
R/W
R/W
R/W
Bit7-0: Xp range register
Bit7-0: Xn range register
Bit7-0: Yp range register
Bit7-0: Yn range register
Xp [6]
Xn [6]
Yp [6]
Yn [6]
Bit 6
R/W
Bit 6
R/W
Bit 6
R/W
Bit 6
R/W
Xp [5]
Xn [5]
Yp [5]
Yn [5]
Bit 5
R/W
Bit 5
R/W
Bit 5
R/W
Bit 5
R/W
Revision 1.09
Xp [4]
Xn [4]
Yp [4]
Yn [4]
Bit 4
Bit 4
Bit 4
Bit 4
R/W
R/W
R/W
R/W
Xp [3]
Xn [3]
Yp [3]
Yn [3]
Bit 3
R/W
Bit 3
R/W
Bit 3
R/W
Bit 3
R/W
Xp [2]
Xn [2]
Yp [2]
Yn [2]
Bit 2
R/W
Bit 2
R/W
Bit 2
R/W
Bit 2
R/W
Xp [1]
Xn [1]
Yp [1]
Yn [1]
Bit 1
Bit 1
Bit 1
Bit 1
R/W
R/W
R/W
R/W
Xp [0]
Xn [0]
Yp [0]
Yn [0]
Bit 0
R/W
Bit 0
R/W
Bit 0
R/W
Bit 0
R/W
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