TLE4998P3 Infineon Technologies, TLE4998P3 Datasheet - Page 28

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TLE4998P3

Manufacturer Part Number
TLE4998P3
Description
IC HALL SENSOR LINEAR SSO-3
Manufacturer
Infineon Technologies
Type
Linear - Programmabler
Datasheet

Specifications of TLE4998P3

Sensing Range
-200mt Trip ~ 200mT Release
Voltage - Supply
4.5 V ~ 5.5 V
Current - Supply
8mA
Current - Output (max)
5mA
Output Type
Digital, PWM (Current)
Operating Temperature
-40°C ~ 150°C
Package / Case
3-SIP, SSO-3-10
Operating Supply Voltage
5 V
Mounting Style
Through Hole
Maximum Operating Temperature
+ 150 C
Minimum Operating Temperature
- 40 C
Maximum Output Current
5 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
SP000412104

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TLE4998P3
Manufacturer:
ON
Quantity:
6 854
Company:
Part Number:
TLE4998P3
Quantity:
5 000
TLE4998P
Calibration
9.1
Calibration Data Memory
When the MEMLOCK bits are programmed (two redundant bits), the memory content is
frozen and may no longer be changed. Furthermore, the programming interface is locked
out and the chip remains in the application mode only. This prevents accidental
programming due to environmental influences.
Column Parity Bits
User-Calibration Bits
Pre-Calibration Bits
Figure 9
EEPROM Map
A matrix parity architecture allows automatic correction of any single-bit error. Each row
is protected by a row parity bit. The sum of bits set including this bit must be an odd
number (ODD PARITY). Each column is additionally protected by a column parity bit.
Each bit in the even positions (0, 2, etc.) of all lines must sum up to an even number
(EVEN PARITY), and each bit in the odd positions (1,3, etc.) must have an odd sum
(ODD PARITY). The parity column must have an even sum (EVEN PARITY).
This mechanism of different parity calculations also protects against many block errors
such as erasing a full line or even the whole EEPROM.
When modifying the application bits (such as Gain, Offset, TC, etc.) the parity bits must
be updated. As for the column bits, the pre-calibration area must be read out and
considered for correct parity generation as well.
Note: A specific programming algorithm must be followed to ensure data retention.
A detailed separate programming specification is available on request.
Data Sheet
28
V 1.0, 2008-07

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