C500IF001 Omron, C500IF001 Datasheet - Page 75

• Manufacturer Part Number: C500IF001
• Description: GPC COMMUNICATIONS ADAPTER
• Manufacturer: Omron

Specifications of C500IF001

• Leaded Process Compatible: No
• Peak Reflow Compatible (260 C): No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Programming Precautions
4-9
Differentiated Conditions
0001
0004
0000
0001
0001
0000
0000
0001
0004
0002
Programming Precautions
0112
0005
0000
0003
0002
0003
0004
0004
Diagram A
Diagram B
Work bits can also be used if differential treatment is necessary for some, but
not all, of the conditions required for execution of an instruction. In this exam-
ple, IR 0100 must be left on continuously as long as IR 0001 is ON and both
IR 0002 and IR 0003 are OFF, or as long as IR 0004 is ON and IR 0005 is
OFF. It must be turned ON for only one cycle each time IR 0000 turns ON
(unless one of the preceding conditions is keeping it ON continuously).
This action is easily programmed by using IR 0112 as a work bit as the oper-
and of the DIFFERENTIATE UP instruction (DIFU(13)). When IR 0000 turns
ON, IR 0112 will be turned ON for one cycle and then be turned OFF the next
cycle by DIFU(13). Assuming the other conditions controlling IR 0100 are not
keeping it ON, the work bit IR 0112 will turn IR 0100 ON for one cycle only.
The number of conditions that can be used in series or parallel is unlimited.
Therefore, use as many conditions as required to draw a clear diagram. Al-
though very complicated diagrams can be drawn with instruction lines almost
forming mazes, there must not be any conditions on instruction lines running
vertically between two other instruction lines. Diagram A shown below, for
example, is not possible, and should be redrawn as diagram B.
The number of times any particular bit can be assigned to conditions is not
limited, so use them as many times as required to simplify your program.
0003
0002
DIFU(13) 0112
Instruction 1
Instruction 2
Instruction 1
Instruction 2
0100
Address
Address Instruction
0000
0001
0002
0003
0004
0005
0006
0007
0008
0009
0000
0001
0002
0003
0004
0005
0006
0007
0008
0009
0010
Instruction
LD
AND
OR
AND
Instruction 1
LD
AND
OR
AND NOT
Instruction 2
LD
DIFU(13)
LD
LD
AND NOT
AND NOT
OR LD
LD
AND NOT
OR LD
OUT
Operands
Operands
Section 4-9
0001
0004
0000
0002
0000
0004
0001
0003
0000
0001
0002
0003
0004
0005
0100
0112
0112
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