LSN2-T/22-D12NG-C Murata Power Solutions Inc, LSN2-T/22-D12NG-C Datasheet - Page 10

• Manufacturer Part Number: LSN2-T/22-D12NG-C
• Description: DC/DC Converter
• Manufacturer: Murata Power Solutions Inc
• Series: LSN2r

Specifications of LSN2-T/22-D12NG-C

• No. Of Outputs: 1
• Input Voltage: 8.3V To 14V
• Power Rating: 112W
• Output Current: 22A
• Approval Bodies: UL, CSA
• Supply Voltage: 14VDC
• Dc / Dc Converter Case Style: SIP
• Dc/dc Converter Mounting: Through Hole
• Product: Non-Isolated / POL
• Output Power: 110 W
• Input Voltage Range: 8.3 V to 14 V
• Input Voltage (nominal): 12 V
• Number Of Outputs: 1
• Output Voltage (channel 1): 0.8 V to 5 V
• Output Current (channel 1): 22 A
• Package / Case Size: SIP
• Output Type: Low Voltage Selectable
• Output Voltage: 0.8 V to 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 12 shows a basic Master (POL A) and Slave (POL B) connected so the
POL B ramps up identically to POL A as shown in timing diagram, Figure 8. RC
network R1 and C1 charge up at a rate set by the R1-C1 time constant, giving
a roughly linear ramp. As POL A reaches 3.3V
B will stop rising. POL A then continues rising until it reaches 5V. R1 should be
signifi cantly smaller than the internal bias current resistor from the Sequence
pin. Start with a 20k: value. We assume that the critical phase is only on
power up therefore there is no provision for ramped power down.
Figure 13 shows a single POL and the same RC network. However, we have
added a FET at Q1 as an up/down control. When V
POL, Q1 is biased on, shorting out the Sequence pin. When Q1’s gate is biased
off, R1 charges C1 and the POL’s output ramps up at the R1-C1 slew rate.
Note: Q1’s gate would typically be controlled from some external digital logic.
If you wish to have a ramped power down (rather than a step down), add a
small resistor in series with Q1’s drain.
Figure 14 shows both a RC ramp on Master POL A and a proportional tracking
divider (R2 and R3) on POL B. We have also added an optional very small
noise fi lter cap at C2. Figure 14’s circuit corresponds roughly to Figure 9’s
timing for power up.
Figure 12. Wiring for Simultaneous Phasing
Figure 13. Self-Ramping Power Up
OUT
(the setpoint of POL B), POL
IN
power is applied to the
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Guidelines for Sequence/Track Applications
[1] Leave the converter’s On/Off Enable control (if installed) in the On setting.
[2] Allow the converter to stabilize (typically less than 20 mS after +V
[3] If you do not use the Sequence/Track pin, leave it open or tied to +V
[4] Observe the Output slew rate relative to the Sequence input. A rough
Normally, you should just leave the On/Off pin open.
power on) before raising the Sequence input. Also, if you wish to have a
ramped power down, leave +V
not simply shut off power.
guide is 2 Volts per millisecond maximum slew rate. If you exceed this
slew rate on the Sequence pin, the converter will simply ramp up at
it’s maximum output slew rate (and will not necessarily track the faster
Sequence input). The reason to carefully consider the slew rate limitation
is in case you want two different POL’s to precisely track each other.
Figure 15. Sequence/Track Simplifi ed Equivalent Schematic
22A Selectable-Output DC/DC Converters
Figure 14. Proportional Phasing
25 Jun 2010
IN
LSN2-T/22-D12
powered all during the down ramp. Do
MDC_LSN2-T/22-D12_B03Δ
Non-isolated, DOSA-SIP,
email: [e-mail]
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IN
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