ADNS-2620 Avago Technologies US Inc., ADNS-2620 Datasheet - Page 13

Optical Mouse Sensor,DIP

ADNS-2620

Manufacturer Part Number
ADNS-2620
Description
Optical Mouse Sensor,DIP
Manufacturer
Avago Technologies US Inc.
Datasheet

Specifications of ADNS-2620

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
516-2238-5
ADNS-2620
Q2073278A
Read Operation
A read operation, meaning data that is going from the
ADNS-2620 to the microcontroller, is always initiated by
the microcontroller and consists of two bytes. The first
byte that contains the address is written by the microcon-
troller and has a “0” as its MSB to indicate data direction.
The second byte contains the data and is driven by the
ADNS-2620. The transfer is synchronized by SCK. SDIO is
changed on falling edges of SCK and read on every rising
Cycle #
Figure 21. Read operation.
Detail "A"
Microcontroller
to ADNS-2620
SDIO handoff
Figure 22. Microcontroller to ADNS-2620 SDIO handoff.
Detail "B"
ADNS-2620 to
Microcontroller
SDIO handoff
Figure 23. ADNS-2620 to microcontroller SDIO handoff.
NOTE:
The 250 ns high state of SCK is the minimum data hold time of the
1
SDIO
ADNS-2620. Since the falling edge of SCK is actually the start of the
next read or write command, the ADNS-2620 will hold the state of D
on the SDIO line until the falling edge of SCK. In both write and read
operations, SCK is driven by the microcontroller.
SCK
SCK
1
0
SDIO
SCK
SDIO
SCK
Released by ADNS-2620
A
2
6
A
1
A
SDIO Driven by Microcontroller
3
5
D
0
A
4
4
60 ns, min
5
A
3
250 ns, min
R/W bit of next address
6
A
160 ns, max
2
Driven by microcontrolle r
250 ns, min
A
0
7
A
1
100 µs, min
t
HOLD
A
0
0
8
Detail "A"
0 ns, min
edge of SCK. The microcontroller must go to a High-Z state
after the last address data bit. The ADNS-2620 will go to
the High-Z state after the last data bit. Another thing
to note during a read operation is that SCK needs to be
delayed after the last address data bit to ensure that the
ADNS-2620 has at least 100 µs to prepare the requested
data. This is shown in the timing diagrams below (See
Figures 21 to 23).
D
9
7
10
D
6
Hi-Z
11
D
5
SDIO Driven by ADNS-2620
250 ns, max
12
D
160 ns, min
D
4
7
13
D
3
D
6
250 ns, max
14
D
2
15
D
1
16
D
Detail "B"
0

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