ADNS-2700 Avago Technologies US Inc., ADNS-2700 Datasheet - Page 15

• Manufacturer Part Number: ADNS-2700
• Description: USB SoC 3B Optical Sensor
• Manufacturer: Avago Technologies US Inc.

Specifications of ADNS-2700

• Supply Voltage Range Dc: 4V To 5.25V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 516-2297-5

OTP Byte Read Operation
OTP read operation flow chart is shown in Figure 17.
1. Set OTP Clock enable bit in OTP_CLOCK register, 0x42:
2. Set OTP enable bit in OTP_CONFIG register, 0x51: OTP_
3. Write the OTP register address byte to OTP_ADDR
4. Set read enable bit in OTP_CTRL register, 0x54 to enable
5. Read the read enable bit status in OTP_CTRL register,
6. Read the OTP data byte from OTP_DATA register, 0x53
7. Repeat Step 2 for more OTP read operations
Figure 17. OTP Byte Read Flow Chart
15
0x51: REGA_OTP_CONFIG[0]=1
0x52: REGA_OTP_ADDR[7:0]
0x54: REGA_OTP_CTRL[1]=1
0x54: REGA_OTP_CTRL[1]
0x53: REGA_OTP_DATA[7:0]
OTP_CLOCK_EN = 1.
EN = 1.
register, 0x52.
write command to OTP: RD = 1.
0x54. If RD = 1, repeat reading the bit status until it is
clear. Read the OTP data byte from OTP_DATA register,
0x53 to complete the OTP read operation.
to complete the OTP read operation.
Read OTP program bit
Write OTP enable bit
Write OTP addr byte
Write OTP read bite
Read OTP data
OTP read done
bit = 0?
bytes?
more
Done
Start
Yes
No
Yes
No
OTP Lock Operation
OTP lock operation MUST be performed once OTP write to
OTPLOCK1 register for the sensor to function. DO not reset
or power up the chip right after OTP write to OTPLOCK1
register, otherwise the chip will be malfunction. The OTP
lock operation flow chart is shown in Figure 18.
1. Set OTP Clock enable bit in OTP_CLOCK register, 0x42:
2. After OTP write to OTPLOCK1 register, set OTP enable
3. Set OTP lock bit in OTP_CTRL register, 0x54 to enable
4. Read the OTP lock bit status in OTP_CTRL register, 0x54.
5. Read the lock status and CRC bits in OTP_CTRLSTAT
6. If Step 4b is repeated up to 10 times, OTP lock operation
Figure 18. OTP Byte Lock Flow Chart
0x51: REGA_OTP_CONFIG[0]=1
0x54: REGA_OTP_CTRL[2] or [3]=1
0x54: REGA_OTP_CTRL[2] or [3]
0x58: REGA_OTP_CTRLSTAT[4] or [6]
0x58: REGA_OTP_CTRLSTAT[5] or [7]
OTP_CLOCK_EN = 1
bit in OTP_CONFIG register, 0x51: OTP_EN = 1.
OTP lock command: LOCK_L1 = 1.
If LOCK_L1 = 1, repeat reading the bit status until it is
clear.
register, 0x58.
a. If both L1_LOCK_OK and L1_CRC_OK = 1, OTP lock
b. If either L1_LOCK_OK or L1_CRC_OK = 0, repeat Step
is failed and the chip is confirmed as defective unit.
operation is completed.
2 until both bits are set.
Repeat = Repeat + 1
Repeat = 10?
OTP write fail
Bad Chip
No
Yes
No
Write OTP enable bit
Read lock status bit
Read CRC status bit
Write OTP lock bit
Read OTP lock bit
lock & crc = 1?
Repeat = 1
more lock?
bit = 0?
OTP lock
Done
Start
Yes
Yes
No
Yes
No