ADNS-7530 Avago Technologies US Inc., ADNS-7530 Datasheet - Page 18

• Manufacturer Part Number: ADNS-7530
• Description: Optical Mouse Sensor,DIP
• Manufacturer: Avago Technologies US Inc.

Specifications of ADNS-7530

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

There are minimum timing requirements between read and write commands on the serial port.
Figure 1 . Timing between two write commands
If the rising edge of the SCLK for the last data bit of the second write command occurs before the required delay
(tSWW), then the first write command may not complete correctly.
Figure 0. Timing between write and read commands
If the rising edge of SCLK for the last address bit of the read command occurs before the required delay (tSWR), the
write command may not complete correctly.
Figure 1. Timing between read and either write or subsequent read commands
During a read operation SCLK should be delayed at least tSRAD after the last address data bit to ensure that the ADNS-
7530 has time to prepare the requested data. The falling edge of SCLK for the first address bit of either the read or
write command must be at least tSRR or tSRW after the last SCLK rising edge of the last data bit of the previous read
operation.
Burst Mode Operation
Burst mode is a special serial port operation mode that may be used to reduce the serial transaction time for a motion
read. The speed improvement is achieved by continuous data clocking to or from multiple registers without the need
to specify the register address, and by not requiring the normal delay period between data bytes.
Burst mode is activated by reading the Motion_Burst register. The ADNS-7530 will respond with the contents of the
Motion, Delta_X_L, Delta_Y_L, Delta_XY_H, SQUAL, Shutter_Upper, Shutter_Lower and Maximum_Pixel registers in
that order. The burst transaction can be terminated anywhere in the sequence after the Delta_X value by bringing the
NCS pin high. After sending the register address, the micro-controller must wait t
All data bits can be read with no delay between bytes by driving SCLK at the normal rate. The data are latched into the
output buffer after the last address bit is received. After the burst transmission is complete, the micro-controller must
raise the NCS line for at least t
NCS, even for a second burst transmission.
Figure . Motion Burst Timing
18
SCLK
SCLK
SCLK
SCLK
equired timing between ead and rite ommands
Motion_Burst Register Address
Address
Address
Address
Write Operation
Write Operation
First Read Operation
BEXIT
Data
Data
t
SRAD
to terminate burst mode. The serial port is not available for use until it is reset with
Read First Byte
t
SRAD
Read Second Byte
Address
t
t
SWW
SWR
Write Operation
Data
Read Third Byte
Address
Data
Next Read
Operation
t
SRW
SRAD
& t
SRR
Address
and then begin reading data.