AEAT-7000-1GSD0 Avago Technologies US Inc., AEAT-7000-1GSD0 Datasheet - Page 3

• Manufacturer Part Number: AEAT-7000-1GSD0
• Description: Abs,13 Bit,serial,100C,8mm
• Manufacturer: Avago Technologies US Inc.
• Series: AEAT-7000r

Specifications of AEAT-7000-1GSD0

• Encoder Type: Optical
• Output Type: Gray Code (Absolute)
• Pulses Per Revolution: 1024
• Voltage - Supply: 5VDC
• Actuator Type: 8mm Open Center
• Detent: No
• Built In Switch: No
• Mounting Type: Chassis Mount
• Orientation: Right Angle
• Termination Style: Terminal Pins
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Rotational Life (cycles Min): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Functional Description
Background
The 13 signal channels are set up as:
Two precision defining Signal (A0, A09), which are 90°
electrical shifted sine, cosine signals. These are condi-
tioned to be compensated for offset and gain errors. After
conditioning they are on chip interpolated of 4bits.
11 analog (A1 – A11) channels which are directly digitized
by precision comparators with hysteresis tracking. The
digitized signals are called D1-D11. Internal correction
and synchronization module allows the composition of a
true 1bit Gray code by merging the data bits of A1-A11
and Sin/Cosine.
There is a Gray code correction feature for this encoder.
This Gray code correction can be disabled/ enabled by the
pin KORR.
The gain and offset conditioning value of the sine and
cosine signals are preloaded on-chip by factory this will
compensate for mechanical sensor misalignment error.
Signal channels A1-A11
The photocurrent of the photo diodes is fed into a trans-im-
pedance amplifier. The analog output of the amplifier has
a voltage swing of (dark/light) about 1.3V. Every output is
transformed by precision comparators into digital signals
(D1-D11). The threshold is at VDD/2 (=Analog-reference),
regulated by the sin/cosine channel.
Monitor channel with LED control at Pin LEDR and LERR
The analog output signal of the monitor channel is
regulated by the LED current. An internal bipolar transis-
tor sets this level to VDD/2 (control voltage at pin (LEDR).
Thus the signal swing of each output is symmetrical to
VDD/2 (=Analog-reference)
The error bit at pin LERR is triggered if the Ve of the internal
bipolar transistor is larger than VDD/2.
Signal channel A0, A09 with signal conditioning and
calibration
These two channels give out a sine and cosine wave,
which are 90 degree phase shifted. These signals have
amplitudes which are almost constant due to the LED
current monitoring. Due to amplifier mismatch and me-
chanical misalignment, the signals have gain and offset
errors. These errors are eliminated by an adaptive signal
conditioning circuitry. The conditioning value are on-chip
preprogrammed by factory. The analog output signals of
A0 and A09 are supplied as true-differential voltage with
a peak-to-peak value of 1.0V at the pins A09P, A09N, A0P,
A0N.
3
Interpolator for channels A0, A09
A0 channel will digitize to form D0 and the LSB bit (D-1)
will generate from the interpolator. The D0 to D-1will be
synchronize with the 11-bit data to D12…D0 to form a
13bit absolute position.
The channels A0, A09 and A1~A11 have very high dynamic
bandwidth, which allows a real time monotone 12-bit
Gray code at 12000RPM.
LSB gray code correction (Pin KORR)
This function block synchronizes the switching points for
the 11-bit Gray code of the digital signals D1 to D11 with
D0 and D09 (digitized signal of A0 and A09).
This Gray code correction only works for the 12-bit
MSB(4096 step per revolution). The correction is not for
the interpolated bits
Gray code correction can be switched on or off by putting
the pin KORR = 1 (on) or = 0 (off ).
MSBINV and DOUT Pins
The serial interface consists a shift register. The most sig-
nificant bit, MSB (D11) will always be sent first to DOUT.
The MSB can be inverted (change code direction) by using
pin MSBINV. Setting MSBINV to high state, output data will
be counting in another direction.
From top view, if code wheel turning clock wise output
data will be increment up, if MSBINV set to high state,
output data will be counting another direction.
If code wheel turning counter-clock wise the output data
will be decrement, if the MSBINV set to high state, output
data will be counting up.
DIN and NSL Pins
The serial input DIN allows the configuration as ring
register for multiple transmissions or for cascading 2 or
more encoders. DIN is the input of the shift register that
shifts the data to DOUT.
The NSL pin controls the shift register, to switch it between
load (1) or shift (0) mode. Under load mode, DOUT will
give the logic of the MSB, i.e., D11.
Under shift mode (0), coupled with the SCL, the register
will be clocked, and gives out the serial word output bit by
bit. As the clock frequency can be up to 16MHz, the trans-
mission of the full 13-bit word can be done within 1us.
Valid data of DOUT should be read when the SCL clock is
low. Please refer to timing diagram (Figure 1).